94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Based on:
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*
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* ----------------------------------------------------------------------------
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*
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* dm644x_emac.h
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*
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* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
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*
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* Copyright (C) 2005 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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*
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* Modifications:
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* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
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*/
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#ifndef _DM644X_EMAC_H_
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#define _DM644X_EMAC_H_
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#include <asm/arch/hardware.h>
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#ifdef CONFIG_SOC_DM365
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#define EMAC_BASE_ADDR (0x01d07000)
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#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
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#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
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#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
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#define DAVINCI_EMAC_VERSION2
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#elif defined(CONFIG_SOC_DA8XX)
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#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
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#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
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#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
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#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
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#define DAVINCI_EMAC_VERSION2
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#else
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#define EMAC_BASE_ADDR (0x01c80000)
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#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
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#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
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#define EMAC_MDIO_BASE_ADDR (0x01c84000)
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#endif
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#ifdef CONFIG_SOC_DM646X
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#define DAVINCI_EMAC_VERSION2
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#define DAVINCI_EMAC_GIG_ENABLE
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#endif
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#ifdef CONFIG_SOC_DM646X
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ 76500000
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
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#elif defined(CONFIG_SOC_DM365)
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ 121500000
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
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#elif defined(CONFIG_SOC_DA8XX)
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
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#else
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
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#endif
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#define PHY_KSZ8873 (0x00221450)
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int ksz8873_is_phy_connected(int phy_addr);
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int ksz8873_get_link_speed(int phy_addr);
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int ksz8873_init_phy(int phy_addr);
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int ksz8873_auto_negotiate(int phy_addr);
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#define PHY_LXT972 (0x001378e2)
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int lxt972_is_phy_connected(int phy_addr);
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int lxt972_get_link_speed(int phy_addr);
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int lxt972_init_phy(int phy_addr);
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int lxt972_auto_negotiate(int phy_addr);
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#define PHY_DP83848 (0x20005c90)
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int dp83848_is_phy_connected(int phy_addr);
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int dp83848_get_link_speed(int phy_addr);
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int dp83848_init_phy(int phy_addr);
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int dp83848_auto_negotiate(int phy_addr);
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#define PHY_ET1011C (0x282f013)
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int et1011c_get_link_speed(int phy_addr);
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#endif /* _DM644X_EMAC_H_ */
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