443 lines
8.9 KiB
C
Executable File
443 lines
8.9 KiB
C
Executable File
/**
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NVT mmc function
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Register settings
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@file na51055_mmcreg.h
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#ifndef _SDIO_REG_H
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#define _SDIO_REG_H
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#include <mach/rcw_macro.h>
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#define SDIO_SCATTER_DMA 1
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#define SDIO_CMD_REG_OFS 0x00
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union SDIO_CMD_REG {
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uint32_t reg;
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struct {
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unsigned int CMD_IDX:6;
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unsigned int NEED_RSP:1;
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unsigned int LONG_RSP:1;
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unsigned int RSP_TIMEOUT_TYPE:1;
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unsigned int CMD_EN:1;
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unsigned int SDC_RST:1;
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unsigned int ENABLE_SDIO_INT_DETECT:1;
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unsigned int ENABLE_VOL_SWITCH_DET:1;
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unsigned int ENABLE_EMMC_BOOT:1;
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unsigned int EMMC_BOOT_ACK:1;
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unsigned int EMMC_BOOT_MODE:1;
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unsigned int EMMC_BOOT_CLK:1;
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unsigned int Reserved0:15;
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} bit;
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};
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#define SDIO_ARGU_REG_OFS 0x04
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union SDIO_ARGU_REG {
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uint32_t reg;
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struct {
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unsigned int ARGUMENT:32;
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} bit;
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};
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#define SDIO_RSP0_REG_OFS 0x08
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union SDIO_RSP0_REG {
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uint32_t reg;
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struct {
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unsigned int RSP:32;
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} bit;
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};
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#define SDIO_RSP1_REG_OFS 0x0C
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union SDIO_RSP1_REG {
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uint32_t reg;
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struct {
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unsigned int RSP_3RD_MSB:32;
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} bit;
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};
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#define SDIO_RSP2_REG_OFS 0x10
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union SDIO_RSP2_REG {
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uint32_t reg;
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struct {
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unsigned int RSP_2ND_MSB:32;
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} bit;
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};
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#define SDIO_RSP3_REG_OFS 0x14
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union SDIO_RSP3_REG {
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uint32_t reg;
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struct {
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unsigned int RSP_1ST_MSB:32;
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} bit;
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};
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#define SDIO_RSP_CMD_REG_OFS 0x18
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union SDIO_RSP_CMD_REG {
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uint32_t reg;
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struct {
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unsigned int RSP_CMD_IDX:6;
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unsigned int Reserved0:26;
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} bit;
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};
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#define SDIO_DATA_CTRL_REG_OFS 0x1C
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union SDIO_DATA_CTRL_REG {
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uint32_t reg;
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struct {
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unsigned int Reserved0:6;
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unsigned int DATA_EN:1;
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unsigned int READ_WAIT_EN:1;
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unsigned int SUSPEND_DATA:1;
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unsigned int DIS_SDIO_INT_PERIOD:1;
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unsigned int Reserved1:3;
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unsigned int WAIT_VOL_SWITCH_EN:1;
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unsigned int Reserved2:2;
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unsigned int BLK_SIZE:16;
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} bit;
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};
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#define SDIO_DATA_TIMER_REG_OFS 0x20
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union SDIO_DATA_TIMER_REG {
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uint32_t reg;
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struct {
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unsigned int TIMEOUT:32;
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} bit;
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};
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#define SDIO_VOL_SWITCH_TIMER_REG_OFS 0x24
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union SDIO_VOL_SWITCH_TIMER_REG {
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uint32_t reg;
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struct {
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unsigned int VOL_TIMEOUT:12;
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unsigned int Reserved1:20;
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} bit;
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};
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#define SDIO_STATUS_REG_OFS 0x28
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union SDIO_STATUS_REG {
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uint32_t reg;
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struct {
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unsigned int RSP_CRC_FAIL:1;
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unsigned int DATA_CRC_FAIL:1;
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unsigned int RSP_TIMEOUT:1;
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unsigned int DATA_TIMEOUT:1;
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unsigned int RSP_CRC_OK:1;
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unsigned int DATA_CRC_OK:1;
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unsigned int CMD_SENT:1;
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unsigned int DATA_END:1;
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unsigned int SDIO_INT:1;
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unsigned int READ_WAIT:1;
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unsigned int CARD_BUSY2READY:1;
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unsigned int VOL_SWITCH_END:1;
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unsigned int VOL_SWITCH_TIMEOUT:1;
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unsigned int RSP_VOL_SWITCH_FAIL:1;
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unsigned int VOL_SWITCH_GLITCH:1;
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unsigned int EMMC_BOOT_ACK_RECEIVE:1;
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unsigned int EMMC_BOOT_ACK_TIMEOUT:1;
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unsigned int EMMC_BOOT_END:1;
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unsigned int EMMC_BOOT_ACK_ERROR:1;
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unsigned int DMA_ERROR:1;
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unsigned int Reserved0:12;
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} bit;
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};
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#define SDIO_INT_MASK_REG_OFS 0x30
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union SDIO_INT_MASK_REG {
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uint32_t reg;
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struct {
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unsigned int RSP_CRC_FAIL_INT_EN:1;
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unsigned int DATA_CRC_FAIL_INT_EN:1;
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unsigned int RSP_TIMEOUT_INT_EN:1;
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unsigned int DATA_TIMEOUT_INT_EN:1;
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unsigned int RSP_CRC_OK_INT_EN:1;
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unsigned int DATA_CRC_OK_INT_EN:1;
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unsigned int CMD_SENT_INT_EN:1;
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unsigned int DATA_END_INT_EN:1;
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unsigned int SDIO_INT_INT_EN:1;
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unsigned int READ_WAIT_INT_EN:1;
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unsigned int CARD_BUSY2READY_INT_EN:1;
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unsigned int VOL_SWITCH_END_INT_EN:1;
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unsigned int VOL_SWITCH_TIMEOUT_INT_EN:1;
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unsigned int RSP_VOL_SWITCH_FAIL_INT_EN:1;
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unsigned int VOL_SWITCH_GLITCH_INT_EN:1;
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unsigned int EMMC_BOOT_ACK_RECEIVE_INT_EN:1;
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unsigned int EMMC_BOOT_ACK_TIMEOUT_INT_EN:1;
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unsigned int EMMC_BOOT_END_INT_EN:1;
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unsigned int EMMC_BOOT_ACK_ERROR_INT_EN:1;
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unsigned int Reserved0:13;
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} bit;
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};
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#define SDIO_CLOCK_CTRL_REG_OFS 0x38
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union SDIO_CLOCK_CTRL_REG {
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uint32_t reg;
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struct {
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unsigned int Reserved0:8;
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unsigned int CLK_AUTOGATE_HIGH:1;
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unsigned int Reserved1:1;
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unsigned int CLK_DIS:1;
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unsigned int Reserved2:21;
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} bit;
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};
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#define SDIO_BUS_WIDTH_REG_OFS 0x3C
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union SDIO_BUS_WIDTH_REG {
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uint32_t reg;
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struct {
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unsigned int BUS_WIDTH:2;
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unsigned int Reserved0:30;
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} bit;
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};
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#define SDIO_BUS_STATUS_REG_OFS 0x40
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union SDIO_BUS_STATUS_REG {
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uint32_t reg;
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struct {
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unsigned int CARD_BUSY:1;
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unsigned int BUS_STS_CMD:1;
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unsigned int Reserved0:6;
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unsigned int BUS_STS_D0:1;
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unsigned int BUS_STS_D1:1;
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unsigned int BUS_STS_D2:1;
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unsigned int BUS_STS_D3:1;
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unsigned int BUS_STS_D4:1;
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unsigned int BUS_STS_D5:1;
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unsigned int BUS_STS_D6:1;
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unsigned int BUS_STS_D7:1;
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unsigned int Reserved1:16;
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} bit;
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};
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#define SDIO_CLOCK_CTRL2_REG_OFS 0x44
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union SDIO_CLOCK_CTRL2_REG {
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uint32_t reg;
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struct {
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unsigned int OUTDLY_SEL:6;
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unsigned int Reserved0:10;
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unsigned int INDLY_SEL:6;
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unsigned int Reserved1:10;
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} bit;
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};
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#define SDIO_EMMC_BOOT_ACK_TIMER_REG_OFS 0x48
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union SDIO_EMMC_BOOT_ACK_TIMER_REG {
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uint32_t reg;
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struct {
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unsigned int TIMEOUT:24;
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unsigned int Reserved0:8;
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} bit;
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};
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#define SDIO_PHY_REG_OFS 0x4C
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union SDIO_PHY_REG {
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uint32_t reg;
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struct {
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unsigned int PHY_SW_RST:1;
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unsigned int Reserved0:3;
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unsigned int BLK_FIFO_EN:1;
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unsigned int Reserved1:27;
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} bit;
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};
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#define SDIO_DLY0_REG_OFS 0x50
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union SDIO_DLY0_REG {
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uint32_t reg;
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struct {
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unsigned int Reserved0:12;
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unsigned int SAMPLE_CLK_EDGE:1;
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unsigned int SRC_CLK_SEL:1;
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unsigned int PAD_CLK_SEL:1;
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unsigned int Reserved1:17;
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} bit;
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};
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#define SDIO_DLY1_REG_OFS 0x54
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union SDIO_DLY1_REG {
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uint32_t reg;
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struct {
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unsigned int Reserved0:28;
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unsigned int DATA_READ_DLY:2;
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unsigned int Reserved1:2;
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} bit;
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};
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#define SDIO_DLY2_REG_OFS 0x58
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union SDIO_DLY2_REG {
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uint32_t reg;
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struct {
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unsigned int DET_DATA_OUT:32;
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} bit;
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};
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#define SDIO_DLY3_REG_OFS 0x5C
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union SDIO_DLY3_REG {
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uint32_t reg;
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struct {
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unsigned int DET_CLR:1;
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unsigned int Reserved0:31;
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} bit;
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};
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#define SDIO_DLY4_REG_OFS 0x60
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union SDIO_DLY4_REG {
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uint32_t reg;
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struct {
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unsigned int PHASE_COMP_EN:16;
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unsigned int Reserved0:16;
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} bit;
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};
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#define SDIO_DLY5_REG_OFS 0x64
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union SDIO_DLY5_REG {
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uint32_t reg;
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struct {
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unsigned int Reserved0:4;
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unsigned int OUT_DLY_EN:1;
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unsigned int DATA_OUT_DLY_INV:1;
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unsigned int CMD_OUT_DLY_INV:1;
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unsigned int Reserved1:1;
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unsigned int OUT_DLY_SEL:5;
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unsigned int Reserved2:19;
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} bit;
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};
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#define SDIO_DATA_PORT_REG_OFS 0x100
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union SDIO_DATA_PORT_REG {
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uint32_t reg;
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struct {
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unsigned int FIFO:32;
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} bit;
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};
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#define SDIO_DATA_LENGTH_REG_OFS 0x104
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union SDIO_DATA_LENGTH_REG {
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uint32_t reg;
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struct {
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unsigned int LENGTH:26;
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unsigned int Reserved0:6;
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} bit;
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};
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#define SDIO_FIFO_STATUS_REG_OFS 0x108
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union SDIO_FIFO_STATUS_REG {
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uint32_t reg;
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struct {
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unsigned int FIFO_CNT:6;
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unsigned int Reserved0:2;
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unsigned int FIFO_EMPTY:1;
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unsigned int FIFO_FULL:1;
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unsigned int Reserved1:22;
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} bit;
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};
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#define SDIO_FIFO_CONTROL_REG_OFS 0x10C
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union SDIO_FIFO_CONTROL_REG {
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uint32_t reg;
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struct {
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unsigned int FIFO_EN:1;
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unsigned int FIFO_MODE:1;
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unsigned int FIFO_DIR:1;
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unsigned int Reserved0:29;
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} bit;
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};
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#define SDIO_FIFO_SWITCH_REG_OFS 0x1B0
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union SDIO_FIFO_SWITCH_REG {
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uint32_t reg;
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struct {
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unsigned int Reserved0:4;
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unsigned int FIFO_SWITCH_DLY:1;
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unsigned int Reserved1:27;
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} bit;
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};
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#if (SDIO_SCATTER_DMA)
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#define SDIO_DMA_DES_START_ADDR_REG_OFS 0x110
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union SDIO_DMA_DES_START_ADDR_REG {
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uint32_t reg;
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struct {
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unsigned int DES_ADDR:31;
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unsigned int Reserved0:1;
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} bit;
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};
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#define SDIO_DMA_DES_CURR_ADDR_REG_OFS 0x114
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union SDIO_DMA_DES_CURR_ADDR_REG {
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uint32_t reg;
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struct {
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unsigned int DRAM_ADDR:31;
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unsigned int Reserved0:1;
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} bit;
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};
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#define SDIO_DMA_ERROR_STS_REG_OFS 0x118
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union SDIO_DMA_ERROR_STS_REG {
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uint32_t reg;
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struct {
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unsigned int DMA_ERR_STS:2;
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unsigned int DMA_LEN_MISMATCH:1;
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unsigned int Reserved0:29;
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} bit;
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};
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#define SDIO_DES_LINE_REG_OFS 0x00
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union SDIO_DES_LINE_REG {
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uint32_t reg;
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struct {
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unsigned int DMA_DES_VALID:1;
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unsigned int DMA_DES_END:1;
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unsigned int Reserved0:2;
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unsigned int DMA_DES_ACT:2;
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unsigned int Reserved1:26;
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} bit;
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};
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#define SDIO_DES_LINE1_REG_OFS 0x04
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union SDIO_DES_LINE1_REG {
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uint32_t reg;
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struct {
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unsigned int DMA_DES_DATA_LEN:26;
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unsigned int Reserved0:6;
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} bit;
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};
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#define SDIO_DES_LINE2_REG_OFS 0x08
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union SDIO_DES_LINE2_REG {
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uint32_t reg;
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struct {
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unsigned int DMA_DES_DATA_ADDR:32;
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} bit;
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};
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#else
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#define SDIO_DMA_START_ADDR_REG_OFS 0x110
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union SDIO_DMA_START_ADDR_REG {
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uint32_t reg;
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struct {
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unsigned int DRAM_ADDR:31;
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unsigned int Reserved0:1;
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} bit;
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};
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#define SDIO_DMA_CURR_ADDR_REG_OFS 0x114
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union SDIO_DMA_CURR_ADDR_REG {
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uint32_t reg;
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struct {
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unsigned int DRAM_ADDR:31;
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unsigned int Reserved0:1;
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} bit;
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};
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#endif
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#endif
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