573 lines
18 KiB
C
Executable File
573 lines
18 KiB
C
Executable File
/**
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NVT mmc function
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Define parameters and initial register value
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@file na51000_mmchost.h
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2016. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#ifndef _SDIO_HOST_H
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#define _SDIO_HOST_H
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#include <mach/rcw_macro.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/cpufreq.h>
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#include <linux/mmc/host.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/mmc.h>
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#include <linux/printk.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <plat/nvt-gpio.h>
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#include <plat/top.h>
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#include <plat/pad.h>
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#include <plat/nvt-mmc.h>
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#include <plat/hardware.h>
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#include "na51055_mmcreg.h"
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/*pll.h*/
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#define SDIO_CLK 34 /* SDIO clock*/
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#define SDIO2_CLK 35 /* SDIO2 clock*/
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#define SDIO3_CLK 46 /* SDIO3 clock*/
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/**********************************************************************/
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/* Definitions */
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/**********************************************************************/
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/*
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SDIO host number encoding.
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*/
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#define SDIO_HOST_ID_1 (0) /* SDIO host*/
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#define SDIO_HOST_ID_2 (1) /* SDIO2 host*/
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#define SDIO_HOST_ID_3 (2) /* SDIO3 host*/
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#define SDIO_HOST_ID_COUNT (3) /* SDIO host count*/
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/*
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SDIO send command execution result.
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Encoding of sdiohost_sendcmd() result.
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*/
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#define SDIO_HOST_CMD_OK (0) /* command execution OK*/
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#define SDIO_HOST_RSP_TIMEOUT (-1) /* response timeout*/
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#define SDIO_HOST_RSP_CRCFAIL (-2) /* response CRC fail*/
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#define SDIO_HOST_CMD_FAIL (-3) /* command fail*/
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/*
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SDIO data transfer result.
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Encoding of sdiohost_waitdataend() result.
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*/
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#define SDIO_HOST_DATA_OK (0) /* data transfer OK*/
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#define SDIO_HOST_DATA_TIMEOUT (-1) /* data block timeout*/
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#define SDIO_HOST_DATA_CRCFAIL (-2) /* data block CRC fail*/
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#define SDIO_HOST_DATA_FAIL (-3) /* data transfer fail*/
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#define SDIO_HOST_BOOT_ACK_OK (0)
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#define SDIO_HOST_BOOT_ACK_TIMEOUT (-1)
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#define SDIO_HOST_BOOT_ACK_ERROR (-2)
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#define SDIO_HOST_BOOT_END (0)
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#define SDIO_HOST_BOOT_END_ERROR (-1)
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/*
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SDIO IO interrupt
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sdiohost_waitio() result
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*/
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#define SDIO_IO_INT_OK (0) /* IO interrupt ok*/
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#define SDIO_IO_INT_FAIL (-1) /* IO interrupt fail*/
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/*
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SDIO Support Voltage
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*/
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#define VOLTAGE_1800 (1800)
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#define VOLTAGE_3300 (3300)
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/*
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User mode pad driving definition
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*/
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#define PAD_DRIVING_5MA 5
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#define PAD_DRIVING_10MA 10
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#define PAD_DRIVING_15MA 15
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#define PAD_DRIVING_20MA 20
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#define PAD_DRIVING_25MA 25
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#define PAD_DRIVING_30MA 30
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#define PAD_DRIVING_35MA 35
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#define PAD_DRIVING_40MA 40
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#define PAD_DRIVING_6MA 6
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#define PAD_DRIVING_16MA 16
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#define PAD_DRIVING_4MA 4
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#define PAD_DRIVING_8MA 8
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/*
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SDIO response type
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@note for sdiohost_sendcmd()
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*/
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typedef enum {
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SDIO_HOST_RSP_NONE, /* No response*/
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SDIO_HOST_RSP_SHORT, /* Short response*/
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SDIO_HOST_RSP_LONG, /* Long response*/
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SDIO_HOST_RSP_SHORT_TYPE2, /* Short response timeout is 5 bus clock*/
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SDIO_HOST_RSP_LONG_TYPE2, /* Long response timeout is 5 bus clock*/
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SDIO_HOST_RSP_VOLT_DETECT, /* voltage detect response*/
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ENUM_DUMMY4WORD(SDIO_HOST_RESPONSE)
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} SDIO_HOST_RESPONSE;
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#define SDIO_HOST_MAX_VOLT_TIMER (0xFFF) /* max value of voltage switch timer*/
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#define SDIO_DES_TABLE_NUM (128)
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#define SDIO_DES_WORD_SIZE (3) /*descriptor 3 word*/
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#define SDIO_HOST_MAX_DATA_LENGTH (64*1024*1024)
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#define SDIO_HOST_DATA_FIFO_DEPTH (16)
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/*sdio_protocol.h*/
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#define SDIO_HOST_WRITE_DATA (FALSE)
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#define SDIO_HOST_READ_DATA (TRUE)
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/* Command Register Bit*/
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#define SDIO_CMD_REG_INDEX 0x0000003F /* bit 5..0*/
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#define SDIO_CMD_REG_NEED_RSP 0x00000040 /* bit 6*/
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#define SDIO_CMD_REG_LONG_RSP 0x000000C0 /* bit 7*/
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#define SDIO_CMD_REG_RSP_TYPE2 0x00000100 /* bit 8*/
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#define SDIO_CMD_REG_APP_CMD 0x00000000 /* bit x*/
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#define SDIO_CMD_REG_ABORT 0x00000800 /* bit 11*/
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#define SDIO_CMD_REG_VOLTAGE_SWITCH_DETECT 0x00001000 /* bit 12*/
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/* Status/Interrupt Mask Register Bit*/
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#define SDIO_STATUS_REG_RSP_CRC_FAIL 0x00000001 /* bit 0*/
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#define SDIO_STATUS_REG_DATA_CRC_FAIL 0x00000002 /* bit 1*/
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#define SDIO_STATUS_REG_RSP_TIMEOUT 0x00000004 /* bit 2*/
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#define SDIO_STATUS_REG_DATA_TIMEOUT 0x00000008 /* bit 3*/
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#define SDIO_STATUS_REG_RSP_CRC_OK 0x00000010 /* bit 4*/
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#define SDIO_STATUS_REG_DATA_CRC_OK 0x00000020 /* bit 5*/
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#define SDIO_STATUS_REG_CMD_SEND 0x00000040 /* bit 6*/
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#define SDIO_STATUS_REG_DATA_END 0x00000080 /* bit 7*/
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#define SDIO_STATUS_REG_INT 0x00000100 /* bit 8*/
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#define SDIO_STATUS_REG_READWAIT 0x00000200 /* bit 9*/
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#define SDIO_STATUS_REG_EMMC_BOOTACKREV 0x00008000 /* bit 15*/
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#define SDIO_STATUS_REG_EMMC_BOOTACKTOUT 0x00010000 /* bit 16*/
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#define SDIO_STATUS_REG_EMMC_BOOTEND 0x00020000 /* bit 17*/
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#define SDIO_STATUS_REG_EMMC_BOOTACKERR 0x00040000 /* bit 18*/
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#define SDIO_STATUS_REG_DMA_ERR 0x00080000 /* bit 19*/
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#define SDIO_INTMASK_ALL 0x000003FF /* bit 9..0*/
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/* Bus Width Register bit definition*/
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#define SDIO_BUS_WIDTH1 0x00000000 /* bit 1..0 : 0x0*/
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#define SDIO_BUS_WIDTH4 0x00000001 /* bit 1..0 : 0x1*/
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#define SDIO_BUS_WIDTH8 0x00000002 /* bit 1..0 : 0x2*/
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/*end sdio_protocol.h*/
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/* Bus Status Mask Register*/
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#define SDIO_DATA_LVL_MASK 0xF00
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/* sdio.h*/
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/**
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@name SDIO source clock definition
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@note for sdio_setHSClk() and sdio2_setHSClk()
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*/
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#define SDIO_SRC_CLK_20MHZ 0 /* No use*/
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#define SDIO_SRC_CLK_24MHZ 1 /* No use*/
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#define SDIO_SRC_CLK_40MHZ 2 /* Source clock 40Mhz, only for SDIO2*/
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#define SDIO_SRC_CLK_48MHZ 3 /* Source clock 48Mhz, SDIO/SDIO2 support*/
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#define SDIO_SRC_CLK_60MHZ 4 /* No use*/
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#define SDIO_SRC_CLK_80MHZ 5 /* Source clock 80Mhz, only for SDIO*/
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#define SDIO_SRC_CLK_SSPLLMHZ 6 /* No use*/
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#define SDIO_SRC_CLK_SSPLL2MHZ 7 /* No use*/
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#define SDIO_SRC_CLK_SSPLL3MHZ 8 /* No use*/
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#define SDIO_SRC_CLK_SSPLL4MHZ 9 /* No use*/
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#define SDIO_SRC_CLK_SSPLL5MHZ 10 /* No use*/
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#define SDIO_SRC_CLK_96MHZ 11 /* Source clock 96Mhz, only for SDIO*/
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#define SDIO_SRC_CLK_PLL4 12 /* Source clock PLL4, SDIO/SDIO2 support*/
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/* end sdio.h*/
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/* for nt96650_mmc.c ,the same define */
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/* SDIO_STATUS_REG_RSP_CRC_FAIL , SDIO_STATUS_REG_DATA_CRC_FAIL*/
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#define MMCST_RSP_CRC_FAIL BIT(0)
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#define MMCST_DATA_CRC_FAIL BIT(1)
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#define MMCST_RSP_TIMEOUT BIT(2)
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#define MMCST_DATA_TIMEOUT BIT(3)
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#define MMCST_RSP_CRC_OK BIT(4)
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#define MMCST_DATA_CRC_OK BIT(5)
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#define MMCST_CMD_SENT BIT(6)
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#define MMCST_DATA_END BIT(7)
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#define MMCST_SDIO_INT BIT(8)
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#define MMCST_READ_WAIT BIT(9)
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#define MMCST_CARD_BUSY2READY BIT(10)
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#define MMCST_VOL_SWITCH_END BIT(11)
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#define MMCST_VOL_SWITCH_TIMEOUT BIT(12)
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#define MMCST_RSP_VOL_SWITCH_FAIL BIT(13)
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#define MMCST_VOL_SWITCH_GLITCH BIT(14)
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#define MMCST_EMMC_BOOT_ACK_RECEIVE BIT(15)
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#define MMCST_EMMC_BOOT_ACK_TIMEOUT BIT(16)
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#define MMCST_EMMC_BOOT_END BIT(17)
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#define MMCST_EMMC_BOOT_ACK_ERROR BIT(18)
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#define MMCST_DMA_ERROR BIT(19)
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/* end for nt96650_mmc.c ,the same define*/
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/*
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SDIO voltage switch result.
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Encoding of sdioHost_waitVoltageSwitch() result.
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*/
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typedef enum {
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SDIO_HOST_VOLT_SWITCH_OK, /* voltage switch OK*/
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SDIO_HOST_VOLT_SWITCH_TIMEOUT, /* voltage switch timeout*/
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ENUM_DUMMY4WORD(SDIO_HOST_VOLT_SWITCH_RESULT)
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} SDIO_HOST_VOLT_SWITCH_RESULT;
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/*
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SDIO boot configuration
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SDIO boot configuration fr sdiohost_setbootconfig()
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*/
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/*
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typedef enum
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{
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SDIO_HOST_BOOT_ACK_DIS = 0,
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SDIO_HOST_BOOT_ACK_EN,
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ENUM_DUMMY4WORD(SDIO_HOST_BOOT_ACK)
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} SDIO_HOST_BOOT_ACK;
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typedef enum
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{
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SDIO_HOST_BOOT_MODE_CMDLOW = 0,
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SDIO_HOST_BOOT_MODE_ALT,
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ENUM_DUMMY4WORD(SDIO_HOST_BOOT_ALT)
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} SDIO_HOST_BOOT_ALT;
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typedef enum
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{
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SDIO_HOST_BOOT_CLK_ALWAYS = 0,
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SDIO_HOST_BOOT_CLK_PAUSE,
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ENUM_DUMMY4WORD(SDIO_HOST_BOOT_CLK)
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} SDIO_HOST_BOOT_CLK;
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typedef enum
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{
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SDIO_HOST_BOOT_BUS_WIDTH_1 = 0,
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SDIO_HOST_BOOT_BUS_WIDTH_4,
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SDIO_HOST_BOOT_BUS_WIDHT_8,
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ENUM_DUMMY4WORD(SDIO_HOST_BOOT_BUSWIDTH)
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} SDIO_HOST_BOOT_BUSWIDTH;
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typedef enum
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{
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SDIO_HOST_BOOT_SPEED_SDR = 0,
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SDIO_HOST_BOOT_SPEED_DDR,
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ENUM_DUMMY4WORD(SDIO_HOST_BOOT_DDR)
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} SDIO_HOST_BOOT_DDR;
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struct {
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SDIO_HOST_BOOT_ACK uibootack;
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SDIO_HOST_BOOT_ALT uibootalt;
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SDIO_HOST_BOOT_CLK uibootclk;
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SDIO_HOST_BOOT_BUSWIDTH uibootbuswidth;
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SDIO_HOST_BOOT_DDR uibootddr;
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}SDIO_HOST_BOOT_CONFIG,*PSDIO_HOST_BOOT_CONFIG;
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*/
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typedef enum {
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SDIO_HOST_SETPOWER_VOL_3P3 = 0,
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SDIO_HOST_SETPOWER_VOL_1P8,
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SDIO_HOST_SETPOWER_VOL_0,
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ENUM_DUMMY4WORD(SDIO_HOST_SETPOWER_VOL)
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} SDIO_HOST_SETPOWER_VOL;
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/**
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SDIO Scatter DMA Descriptor
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SDIO Scatter DMA Descriptor
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@note for STRG_EXT_CMD_SDIO_SEG_DES
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*/
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struct STRG_SEG_DES {
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uint32_t uisegaddr; /* segment address*/
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uint32_t uisegsize; /* segment size*/
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};
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typedef enum {
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SDIO_MODE_DS = 25000000,
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SDIO_MODE_HS = 50000000,
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SDIO_MODE_SDR50 = 100000000,
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SDIO_MODE_SDR104 = 208000000,
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ENUM_DUMMY4WORD(SDIO_SPEED_MODE)
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} SDIO_SPEED_MODE;
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enum SDIO_MODE_DRIVING {
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SDIO_DS_MODE_CLK = 0,
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SDIO_DS_MODE_CMD,
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SDIO_DS_MODE_DATA,
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SDIO_HS_MODE_CLK,
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SDIO_HS_MODE_CMD,
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SDIO_HS_MODE_DATA,
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SDIO_SDR50_MODE_CLK,
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SDIO_SDR50_MODE_CMD,
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SDIO_SDR50_MODE_DATA,
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SDIO_SDR104_MODE_CLK,
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SDIO_SDR104_MODE_CMD,
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SDIO_SDR104_MODE_DATA,
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SDIO_MAX_MODE_DRIVING,
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};
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struct mmc_nvt_host {
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struct mmc_command *cmd;
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struct mmc_data *data;
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struct mmc_host *mmc;
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struct clk *clk;
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unsigned int mmc_input_clk;
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void __iomem *base;
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struct resource *mem_res;
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int id;
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int mmc_irq;
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int mmc_cd_irq;
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unsigned char bus_mode;
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unsigned char timing;
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unsigned char data_dir;
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unsigned char voltage_switch;
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u32 status;
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spinlock_t lock;
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/* buffer is used during PIO of one scatterlist segment, and
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* is updated along with buffer_bytes_left. bytes_left applies
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* to all N blocks of the PIO transfer.
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*/
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u8 *buffer;
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u32 buffer_bytes_left;
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u32 bytes_left;
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/*u32 rxdma, txdma;*/
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bool use_dma;
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bool do_dma;
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bool sdio_int;
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/*early data*/
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bool data_early;
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int cd_gpio;
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int ro_gpio;
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int power_en;
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int cp_gpio;
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bool cd_detect_edge;
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bool ro_detect_edge;
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bool power_detect_edge;
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bool cp_gpio_value;
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int max_voltage;
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int cd_state;
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int neg_sample_edge;
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bool need_power_cycle;
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int indly_sel;
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int outdly_sel;
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bool scan_indly_engineering_mode;
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bool force_power_cycle;
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int force_power_cycle_period;
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int power_down_delay_ms; /* delay after card power OFF */
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int power_up_delay_ms; /* delay after card power ON */
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/* Defines pad_driving of each mode, as:
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* DS_MODE_CLK
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* DS_MODE_CMD
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* DS_MODE_DATA
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* HS_MODE_CLK
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* HS_MODE_CMD
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* HS_MODE_DATA
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* SDR50_MODE_CLK
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* SDR50_MODE_CMD
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* SDR50_MODE_DATA
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* SDR104_MODE_CLK
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* SDR104_MODE_CMD
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* SDR104_MODE_DATA
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*/
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u32 pad_driving[SDIO_MAX_MODE_DRIVING];
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u32 pinmux_value;
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/* Scatterlist DMA uses one or more parameter RAM entries:
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* the main one (associated with rxdma or txdma) plus zero or
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* more links. The entries for a given transfer differ only
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* by memory buffer (address, length) and link field.
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*/
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/*struct edmacc_param tx_template;*/
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/*struct edmacc_param rx_template;*/
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unsigned n_link;
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/*u32 links[MAX_NR_SG - 1];*/
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/* For PIO we walk scatterlists one segment at a time. */
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unsigned int sg_len;
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struct scatterlist *sg;
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/* Version of the MMC/SD controller */
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u8 version;
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/* for ns in one cycle calculation */
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unsigned ns_in_one_cycle;
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/* Number of sg segments */
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u8 nr_sg;
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struct completion voltage_switch_complete;
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struct completion tuning_data_end;
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int voltage_switch_timeout;
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unsigned int vuisdio_destab[SDIO_DES_TABLE_NUM * SDIO_DES_WORD_SIZE];
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#ifdef SDIO_SCATTER_DMA
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struct STRG_SEG_DES tmpdestable[SDIO_DES_TABLE_NUM];
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#endif
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};
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/*********************************************************************/
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/* Function protopyes*/
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/*********************************************************************/
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/*
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host related function prototypes
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*/
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extern bool sdiohost_getrdy(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_enclockout(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_disclockout(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_reset(struct mmc_nvt_host *host, uint32_t id);
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extern int sdiohost_sendcmd(struct mmc_nvt_host *host, uint32_t id,
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uint32_t cmd, SDIO_HOST_RESPONSE rsptype, bool beniointdetect);
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extern uint32_t sdiohost_waitdataend(uint32_t id);
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extern SDIO_HOST_VOLT_SWITCH_RESULT sdiohost_waitvoltageswitch(uint32_t id,
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uint32_t uitimeout);
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extern void sdiohost_setarg(struct mmc_nvt_host *host, uint32_t id,
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uint32_t arg);
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extern void sdiohost_getshortrsp(struct mmc_nvt_host *host, uint32_t id,
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uint32_t *prsp);
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extern void sdiohost_getlongrsp(struct mmc_nvt_host *host, uint32_t id,
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uint32_t *prsp3, uint32_t *prsp2, uint32_t *prsp1, uint32_t *prsp0);
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extern void sdiohost_setinten(struct mmc_nvt_host *host, uint32_t id,
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uint32_t bits);
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extern void sdiohost_disinten(struct mmc_nvt_host *host, uint32_t id,
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uint32_t bits);
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extern void sdiohost_setbuswidth(struct mmc_nvt_host *host, uint32_t id,
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uint32_t width);
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extern uint32_t sdiohost_getbuswidth(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_enclkout(struct mmc_nvt_host *host, uint32_t id,
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bool enableflag);
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extern void sdiohost_enclkddr(struct mmc_nvt_host *host, uint32_t id,
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bool bddr);
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extern void sdiohost_setbusclk(struct mmc_nvt_host *host, uint32_t id,
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uint32_t uiclock, uint32_t *ns);
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extern uint32_t sdiohost_getbusclk(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_setclktype(struct mmc_nvt_host *host, uint32_t id,
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bool brisingsample);
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extern void sdiohost_getclktype(struct mmc_nvt_host *host, uint32_t id,
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bool *brisingsample);
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extern void sdiohost_setclkcmdtype(struct mmc_nvt_host *host, uint32_t id,
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bool brisingsample);
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extern uint32_t sdiohost_getblksize(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_setblksize(struct mmc_nvt_host *host, uint32_t id,
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uint32_t size);
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extern void sdiohost_setdatatimeout(struct mmc_nvt_host *host, uint32_t id,
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uint32_t timeout);
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extern void sdiohost_resetdata(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_waitfifoempty(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_clrfifoen(struct mmc_nvt_host *host, uint32_t id);
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extern uint32_t sdiohost_getfifodir(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_setupdatatransferdma(struct mmc_nvt_host *host,
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uint32_t id, uint32_t uidmaaddress,
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uint32_t uidatalength, bool bisread, uint32_t *vuisdio_destab);
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extern void sdiohost_setupdatatransferpio(struct mmc_nvt_host *host,
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uint32_t id, uint32_t uidmaaddress,
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uint32_t uidatalength, bool bisread);
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extern int sdiohost_writeblock(struct mmc_nvt_host *host, uint32_t id,
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uint8_t *pbuf, uint32_t uilength);
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extern int sdiohost_readblock(struct mmc_nvt_host *host, uint32_t id,
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uint8_t *pbuf, uint32_t uilength);
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extern uint32_t sdiohost_setiointen(struct mmc_nvt_host *host, uint32_t id,
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bool ben);
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extern bool sdiohost_getiointen(struct mmc_nvt_host *host, uint32_t id);
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extern int sdiohost_open(struct mmc_nvt_host *host, uint32_t id, int volatge_switch);
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extern int sdiohost_sendsdcmd(struct mmc_nvt_host *host, uint32_t id,
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uint32_t cmdpart, uint32_t param);
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extern void sdiohost_setstatus(struct mmc_nvt_host *host, uint32_t id,
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uint32_t status);
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extern uint32_t sdiohost_getstatus(struct mmc_nvt_host *host, uint32_t id);
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extern void sdiohost_setdesen(uint32_t id, uint32_t uien);
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extern void sdiohost_setdestab(uint32_t id, uint32_t uidesaddr, uint32_t uidesnum,
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uint32_t *vuisdio_destab);
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extern void sdiohost_setpower(struct mmc_nvt_host *host, \
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SDIO_HOST_SETPOWER_VOL vol);
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extern int sdiohost_getpower(struct mmc_nvt_host *host);
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extern uint32_t sdiohost_getdata_status(struct mmc_nvt_host *host, uint32_t id);
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extern u32 sdiohost_set_voltage_switch(struct mmc_nvt_host *host);
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extern int sdiohost_setpaddriving(struct mmc_nvt_host *host, SDIO_SPEED_MODE mode);
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extern void sdiohost_setphyrst(struct mmc_nvt_host *host);
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extern void sdiohost_setphysample(struct mmc_nvt_host *host, bool internal, bool before);
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extern void sdiohost_setinvoutdly(struct mmc_nvt_host *host, bool data_outdly_inv, bool cmd_outdly_inv);
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extern void sdiohost_setphyclkoutdly(struct mmc_nvt_host *host, uint32_t outdly_sel);
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extern void sdiohost_setphyclkindly(struct mmc_nvt_host *host, uint32_t indly_sel);
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extern int sdiohost_tuning_cmd(struct mmc_nvt_host *host, u32 opcode, bool print_pattern_err);
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extern void sdiohost_setphyclrdetval(struct mmc_nvt_host *host);
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extern void sdiohost_setphydetch(struct mmc_nvt_host *host, u32 ch);
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extern int sdiohost_getcmd(struct mmc_nvt_host *host);
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extern void sdiohost_power_switch(struct mmc_nvt_host *host, bool enable);
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extern u32 sdiohost_getphydetout(struct mmc_nvt_host *host);
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extern void sdiohost_setdlyphase_sel(struct mmc_nvt_host *host, u32 sel);
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extern void sdiohost_setphyphase_cmpen(struct mmc_nvt_host *host, u32 sel);
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extern void sdiohost_set_pads(struct mmc_nvt_host *host, PAD_PULL pulltype);
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extern void sdiohost_set_gpios(struct mmc_nvt_host *host, bool dir_out, int value);
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extern void sdiohost_power_down(struct mmc_nvt_host *host);
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extern void sdiohost_power_up(struct mmc_nvt_host *host);
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extern void sdio_copy_info(struct mmc_nvt_host *info);
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extern void sdiohost_power_cycle(struct mmc_nvt_host *host, uint32_t delay_ms);
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extern void sdiohost_setblkfifoen(struct mmc_nvt_host *host, bool enable);
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#endif
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