57 lines
1.4 KiB
ArmAsm
Executable File
57 lines
1.4 KiB
ArmAsm
Executable File
//#include "regdef.h"
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# use CC_CPU2_CPU1_CMDBUF_REG1 to store uboot starting address
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#define CC_CPU2_CPU1_CMDBUF_REG1 0xF07F800C
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#define CPU_TIMER_SETTING 0x00B71B00
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/*
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************************************************************************
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* Multiprocessor Affubuty register, MPIDR (cp15, 0, c0, c0, 5) *
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************************************************************************
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |1|U|Reserved |Cluster|SBZ |CPU|
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* | | | |ID | |ID |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*/
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#define S_MPIDR_U 30
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#define M_MPIDR_U (0x1 << S_MPIDR_U)
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#define S_MPIDR_CLUSTER_ID 8
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#define M_MPIDR_CLUSTER_ID (0xf << S_MPIDR_CLUSTER_ID)
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#define S_MPIDR_CPU_ID 0
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#define M_MPIDR_CPU_ID (0x3 << S_MPIDR_CPU_ID)
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.text
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.section .smp,"ax"
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_smp_:
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ldr r0, =0xF0290000
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ldr r1, ='2'
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str r1, [r0]
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ldr r0, =0xF0290000 /* print $ */
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ldr r1, ='c'
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str r1, [r0]
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ldr r1, ='o'
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str r1, [r0]
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ldr r1, ='r'
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str r1, [r0]
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ldr r1, ='2'
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str r1, [r0]
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LDR r1, =CC_CPU2_CPU1_CMDBUF_REG1 // check core2 entry address ready
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LDR r0, [r1]
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isb
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dsb
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MOV pc, r0
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nop
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nop
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.end
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