201 lines
3.0 KiB
ArmAsm
Executable File
201 lines
3.0 KiB
ArmAsm
Executable File
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.org 0
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.text
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.globl _sram_vector_table
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.extern Reset
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.extern UndefinedHandler
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.extern SWIHandler
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.extern PrefetchAbortHandler
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.extern DataAbortHandler
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.extern ReservedHandler
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.extern IRQHandler
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.extern FIQHandler
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.extern dispatch_interrupt
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.section .vtrs, "ax"
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_sram_vector_table:
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/**
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* vector table
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* ===========================
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* 00 - Reset
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* 04 - Undefined instructions
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* 08 - SWI instructions
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* 0C - prefetch abort
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* 10 - Data abort
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* 14 - Reserved
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* 18 - IRQ interrupts
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* 1C - FIQ interrupts
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*/
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ldr pc, _vectorReset
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ldr pc, _vectorUndefined
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ldr pc, _vectorSWI
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ldr pc, _vectorPrefetchAbort
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ldr pc, _vectorDataAbort
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ldr pc, _vectorReserved
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ldr pc, _vectorIRQ
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ldr pc, _vectorFIQ
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_vectorReset:
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.word Reset
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_vectorUndefined:
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.word UndefinedHandler
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_vectorSWI:
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.word SWIHandler
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_vectorPrefetchAbort:
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.word PrefetchAbortHandler
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_vectorDataAbort:
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.word DataAbortHandler
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_vectorReserved:
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.word ReservedHandler
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_vectorIRQ:
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.word IRQHandler
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_vectorFIQ:
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.word FIQHandler
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Reset:
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ldr r0, =0xF0290000
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ldr r1, ='R'
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str r1, [r0]
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ldr r1, ='S'
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str r1, [r0]
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ldr r1, ='T'
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str r1, [r0]
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reset_block:
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b reset_block
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nop
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UndefinedHandler:
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ldr r0, =0xf0290000
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ldr r1, ='U'
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str r1, [r0]
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ldr r1, ='D'
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str r1, [r0]
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ldr r1, ='F'
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str r1, [r0]
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#udf_block:
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# b udf_block
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subs pc, lr, #4
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nop
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SWIHandler:
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ldr r0, =0xf0290000
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ldr r1, ='S'
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str r1, [r0]
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ldr r1, ='W'
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str r1, [r0]
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ldr r1, ='I'
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str r1, [r0]
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swi_block:
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b swi_block
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nop
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PrefetchAbortHandler:
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ldr r0, =0xf0290000
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ldr r1, ='P'
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str r1, [r0]
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ldr r1, ='R'
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str r1, [r0]
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ldr r1, ='F'
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str r1, [r0]
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#pref_block:
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# b pref_block
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subs pc, lr, #4
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nop
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DataAbortHandler:
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ldr r0, =0xf0290000
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ldr r1, ='A'
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str r1, [r0]
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ldr r1, ='B'
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str r1, [r0]
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ldr r1, ='T'
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str r1, [r0]
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ldr r1, ='T'
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str r1, [r0]
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#abort_block:
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# b abort_block
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subs pc, lr, #4
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nop
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ReservedHandler:
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ldr r0, =0xf0290000
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ldr r1, ='R'
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str r1, [r0]
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ldr r1, ='S'
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str r1, [r0]
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ldr r1, ='V'
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str r1, [r0]
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rsv_block:
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b rsv_block
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nop
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IRQHandler:
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ldr r0, =0xf0290000
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ldr r1, =0x24
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str r1, [r0]
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sub sp, sp, #72
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stmia sp, {r0 - r12}
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add r8, sp, #60
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str r1, [r0]
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stmdb r8, {sp, lr}^
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str r1, [r0]
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str lr, [r8, #0]
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str r1, [r0]
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mrs r6, spsr
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str r1, [r0]
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str r6, [r8, #4]
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str r1, [r0]
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str r0, [r8, #8]
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str r1, [r0]
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ldr r0, =0xf0290000
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ldr r1, ='I'
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str r1, [r0]
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ldr r1, ='R'
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str r1, [r0]
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ldr r1, ='Q'
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str r1, [r0]
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mov r0, sp
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bl dispatch_interrupt
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# mcr p15, 0, sp, c7, c6, 1
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ldmia sp, {r0 - lr}^
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mov r0, r0
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ldr lr, [sp, #60]
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add sp, sp, #72
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subs pc, lr, #4
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nop
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FIQHandler:
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sub sp, sp, #52
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stmia sp, {r0 - r7}
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add r8, sp, #40
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stmdb r8, {sp, lr}^
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str lr, [r8, #0]
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mrs r6, spsr
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str r6, [r8, #4]
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str r0, [r8, #8]
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mov r0, sp
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bl dispatch_interrupt
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ldr r0, =0xf0290000
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ldr r1, ='F'
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str r1, [r0]
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ldr r1, ='I'
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str r1, [r0]
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ldr r1, ='Q'
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str r1, [r0]
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ldmia sp, {r0 - r7}^
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ldr lr, [sp, #40]
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add sp, sp, #52
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subs pc, lr, #4
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nop
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.end
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