288 lines
6.7 KiB
C
Executable File
288 lines
6.7 KiB
C
Executable File
/**
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Provide basic CPU info
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@file soc.c
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/io.h>
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//#include <asm/arch/soc.h>
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#include <asm/arch/clock.h>
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#include <asm/nvt-common/nvt_ivot_optee.h>
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//#include <asm/arch/gpio.h>
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#include <asm/arch/na51102_regs.h>
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#include <asm/arch/IOAddress.h>
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#include <asm/arch/hardware.h>
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#include <linux/sizes.h>
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#include <linux/compiler.h>
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#include <ns16550.h>
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#include <dm.h>
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#ifdef CONFIG_NVT_IVOT_DDR_SLOW_DOWN_SUPPORT
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extern int nvt_ddr_slow_down(void);
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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static struct ns16550_platdata ns16550_com1_pdata = {
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.base = CONFIG_SYS_NS16550_COM1,
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.reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_HSCLK,
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};
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static struct ns16550_platdata ns16550_com2_pdata = {
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.base = CONFIG_SYS_NS16550_COM2,
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.reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_HSCLK,
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};
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static struct ns16550_platdata ns16550_com3_pdata = {
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.base = CONFIG_SYS_NS16550_COM3,
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.reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_HSCLK,
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};
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static struct ns16550_platdata ns16550_com4_pdata = {
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.base = CONFIG_SYS_NS16550_COM4,
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.reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_HSCLK,
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};
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static struct ns16550_platdata ns16550_com5_pdata = {
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.base = CONFIG_SYS_NS16550_COM5,
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.reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_HSCLK,
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};
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static struct ns16550_platdata ns16550_com6_pdata = {
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.base = CONFIG_SYS_NS16550_COM6,
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.reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_HSCLK,
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};
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U_BOOT_DEVICE(ns16550_com1) = {
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"ns16550_serial", &ns16550_com1_pdata
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#ifdef CONFIG_SYS_NS16550_COM2
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"ns16550_serial", &ns16550_com2_pdata
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#endif
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#ifdef CONFIG_SYS_NS16550_COM3
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"ns16550_serial", &ns16550_com3_pdata
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#endif
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#ifdef CONFIG_SYS_NS16550_COM4
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"ns16550_serial", &ns16550_com4_pdata
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#endif
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#ifdef CONFIG_SYS_NS16550_COM5
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"ns16550_serial", &ns16550_com5_pdata
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#endif
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#ifdef CONFIG_SYS_NS16550_COM6
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"ns16550_serial", &ns16550_com6_pdata
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#endif
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};
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#endif
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int serial_preinit(void)
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{
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#if (!(CONFIG_UART2_PINMUX_NONE && CONFIG_UART3_PINMUX_NONE && CONFIG_UART4_PINMUX_NONE && CONFIG_UART5_PINMUX_NONE))
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u32 value;
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#endif
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#ifdef CONFIG_SYS_NS16550_COM2
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#ifdef CONFIG_UART2_PINMUX_CHANNEL_1
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value = readl(IOADDR_TOP_REG_BASE + 0xA8);
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writel(value & ~0x30, IOADDR_TOP_REG_BASE + 0xA8);
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value = readl(IOADDR_TOP_REG_BASE + 0x1C);
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value &= ~0x30;
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writel(value | 0x10, IOADDR_TOP_REG_BASE + 0x1C);
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value = readl(IOADDR_CG_REG_BASE + 0x78);
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writel(value | 0x200000, IOADDR_CG_REG_BASE + 0x78);
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#elif defined(CONFIG_UART2_PINMUX_CHANNEL_2)
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value = readl(IOADDR_TOP_REG_BASE + 0xA0);
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writel(value & ~0x300, IOADDR_TOP_REG_BASE + 0xA0);
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value = readl(IOADDR_TOP_REG_BASE + 0x1C);
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value &= ~0x30;
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writel(value | 0x20, IOADDR_TOP_REG_BASE + 0x1C);
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value = readl(IOADDR_CG_REG_BASE + 0x78);
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writel(value | 0x200000, IOADDR_CG_REG_BASE + 0x78);
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#elif defined(CONFIG_UART2_PINMUX_CHANNEL_3)
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#endif
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#endif
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#ifdef CONFIG_SYS_NS16550_COM3
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#ifdef CONFIG_UART3_PINMUX_CHANNEL_1
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value = readl(IOADDR_TOP_REG_BASE + 0xA8);
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writel(value & ~0x300, IOADDR_TOP_REG_BASE + 0xA8);
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value = readl(IOADDR_TOP_REG_BASE + 0x1C);
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value &= ~0x100;
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writel(value | 0x100, IOADDR_TOP_REG_BASE + 0x1C);
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value = readl(IOADDR_CG_REG_BASE + 0x78);
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writel(value | 0x400000, IOADDR_CG_REG_BASE + 0x78);
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#elif defined(CONFIG_UART3_PINMUX_CHANNEL_2)
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#elif defined(CONFIG_UART3_PINMUX_CHANNEL_3)
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#elif defined(CONFIG_UART3_PINMUX_CHANNEL_4)
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#elif defined(CONFIG_UART3_PINMUX_CHANNEL_5)
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#endif
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#endif
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#ifdef CONFIG_SYS_NS16550_COM4
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#ifdef CONFIG_UART4_PINMUX_CHANNEL_1
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value = readl(IOADDR_TOP_REG_BASE + 0xA8);
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writel(value & ~0xC00, IOADDR_TOP_REG_BASE + 0xA8);
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value = readl(IOADDR_TOP_REG_BASE + 0x1C);
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value &= ~0x3000;
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writel(value | 0x1000, IOADDR_TOP_REG_BASE + 0x1C);
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value = readl(IOADDR_CG_REG_BASE + 0x78);
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writel(value | 0x800000, IOADDR_CG_REG_BASE + 0x78);
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#elif defined(CONFIG_UART4_PINMUX_CHANNEL_2)
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value = readl(IOADDR_TOP_REG_BASE + 0xA8);
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writel(value & ~0x3000, IOADDR_TOP_REG_BASE + 0xA8);
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value = readl(IOADDR_TOP_REG_BASE + 0x1C);
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value &= ~0x3000;
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writel(value | 0x2000, IOADDR_TOP_REG_BASE + 0x1C);
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value = readl(IOADDR_CG_REG_BASE + 0x78);
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writel(value | 0x800000, IOADDR_CG_REG_BASE + 0x78);
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#endif
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#endif
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#ifdef CONFIG_SYS_NS16550_COM5
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#ifdef CONFIG_UART5_PINMUX_CHANNEL_1
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value = readl(IOADDR_TOP_REG_BASE + 0xA4);
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writel(value & ~0x18, IOADDR_TOP_REG_BASE + 0xA4);
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value = readl(IOADDR_TOP_REG_BASE + 0x1C);
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value &= ~0x30000;
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writel(value | 0x10000, IOADDR_TOP_REG_BASE + 0x1C);
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value = readl(IOADDR_CG_REG_BASE + 0x78);
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writel(value | 0x1000000, IOADDR_CG_REG_BASE + 0x78);
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#elif defined(CONFIG_UART5_PINMUX_CHANNEL_2)
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value = readl(IOADDR_TOP_REG_BASE + 0xA8);
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writel(value & ~0x180000, IOADDR_TOP_REG_BASE + 0xA8);
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value = readl(IOADDR_TOP_REG_BASE + 0x1C);
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value &= ~0x30000;
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writel(value | 0x20000, IOADDR_TOP_REG_BASE + 0x1C);
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value = readl(IOADDR_CG_REG_BASE + 0x78);
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writel(value | 0x1000000, IOADDR_CG_REG_BASE + 0x78);
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#endif
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#endif
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#ifdef CONFIG_SYS_NS16550_COM6
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#ifdef CONFIG_UART6_PINMUX_CHANNEL_1
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#elif defined(CONFIG_UART6_PINMUX_CHANNEL_2)
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#endif
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#endif
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return 0;
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}
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void enable_caches(void)
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{
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dcache_enable();
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icache_enable();
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}
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void __weak reset_cpu(unsigned long ignored)
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{
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}
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#ifdef CONFIG_ARCH_MISC_INIT
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#ifdef CONFIG_NOVATEK_PAD
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extern void nvt_pad_init(void);
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#endif
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int arch_misc_init(void)
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{
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#ifdef CONFIG_NOVATEK_PAD
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nvt_pad_init();
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#endif
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return 0;
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}
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#endif
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/*
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* Routine: dram_init
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* Description: sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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#ifdef CONFIG_NVT_IVOT_DDR_SLOW_DOWN_SUPPORT
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// Default not enabled in nvt platform.
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// If specific project needs slow down DDR freq at boot,
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// plz uncomment below line.
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// nvt_ddr_slow_down();
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#endif
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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/*
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* Print board information
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*/
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int checkboard(void)
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{
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return 0;
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}
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/*
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* Print CPU information
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*/
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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printf("CPU: Novatek %s @ %lu MHz\n", _CHIP_NAME_, get_cpu_clk()/1000);
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return 0;
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}
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#endif
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void s_init(void)
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{
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//u32 val;
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/* Do we want to combine ARM_UART_B and STBC_UART_1 on EVB board?
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* NO! So we need set fc040250[bit0] to "0"
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*/
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// val = *(volatile unsigned int *)0xfc040250;
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// if ((val & 0x01) == 0x01) {
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// val &= ~0x01;
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// writel(0x0, 0xfc040250);
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// }
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gd->cpu_clk = get_cpu_clk() * 1000;
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}
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void cpu_cache_initialization(void)
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{
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return;
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}
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u32 nvt_get_chip_id(void)
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{
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unsigned int chip_id;
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chip_id = (readl(IOADDR_TOP_REG_BASE + TOP_VERSION_REG_OFS) >> 16) & 0xFFFF;
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return chip_id;
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}
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