224 lines
7.4 KiB
C
224 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_MMU_H
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#define __KVM_X86_MMU_H
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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#define PT64_PT_BITS 9
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#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
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#define PT32_PT_BITS 10
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#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
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#define PT_WRITABLE_SHIFT 1
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#define PT_USER_SHIFT 2
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#define PT_PRESENT_MASK (1ULL << 0)
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#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
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#define PT_USER_MASK (1ULL << PT_USER_SHIFT)
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#define PT_PWT_MASK (1ULL << 3)
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#define PT_PCD_MASK (1ULL << 4)
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#define PT_ACCESSED_SHIFT 5
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#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
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#define PT_DIRTY_SHIFT 6
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#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
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#define PT_PAGE_SIZE_SHIFT 7
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#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
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#define PT_PAT_MASK (1ULL << 7)
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#define PT_GLOBAL_MASK (1ULL << 8)
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#define PT64_NX_SHIFT 63
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#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
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#define PT_PAT_SHIFT 7
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#define PT_DIR_PAT_SHIFT 12
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#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
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#define PT32_DIR_PSE36_SIZE 4
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#define PT32_DIR_PSE36_SHIFT 13
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#define PT32_DIR_PSE36_MASK \
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(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
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#define PT64_ROOT_5LEVEL 5
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#define PT64_ROOT_4LEVEL 4
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#define PT32_ROOT_LEVEL 2
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#define PT32E_ROOT_LEVEL 3
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#define PT_PDPE_LEVEL 3
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#define PT_DIRECTORY_LEVEL 2
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#define PT_PAGE_TABLE_LEVEL 1
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#define PT_MAX_HUGEPAGE_LEVEL (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES - 1)
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static inline u64 rsvd_bits(int s, int e)
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{
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if (e < s)
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return 0;
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return ((1ULL << (e - s + 1)) - 1) << s;
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}
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void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value);
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void
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reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
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void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots);
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void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
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void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
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bool accessed_dirty, gpa_t new_eptp);
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bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
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int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
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u64 fault_address, char *insn, int insn_len);
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static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
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{
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if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
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return kvm->arch.n_max_mmu_pages -
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kvm->arch.n_used_mmu_pages;
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return 0;
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}
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static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
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{
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if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
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return 0;
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return kvm_mmu_load(vcpu);
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}
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static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
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{
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BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
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return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
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? cr3 & X86_CR3_PCID_MASK
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: 0;
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}
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static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
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{
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return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
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}
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static inline void kvm_mmu_load_cr3(struct kvm_vcpu *vcpu)
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{
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if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
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vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa |
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kvm_get_active_pcid(vcpu));
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}
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/*
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* Currently, we have two sorts of write-protection, a) the first one
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* write-protects guest page to sync the guest modification, b) another one is
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* used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
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* between these two sorts are:
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* 1) the first case clears SPTE_MMU_WRITEABLE bit.
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* 2) the first case requires flushing tlb immediately avoiding corrupting
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* shadow page table between all vcpus so it should be in the protection of
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* mmu-lock. And the another case does not need to flush tlb until returning
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* the dirty bitmap to userspace since it only write-protects the page
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* logged in the bitmap, that means the page in the dirty bitmap is not
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* missed, so it can flush tlb out of mmu-lock.
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*
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* So, there is the problem: the first case can meet the corrupted tlb caused
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* by another case which write-protects pages but without flush tlb
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* immediately. In order to making the first case be aware this problem we let
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* it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit
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* is set, it works since another case never touches SPTE_MMU_WRITEABLE bit.
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*
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* Anyway, whenever a spte is updated (only permission and status bits are
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* changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes
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* readonly, if that happens, we need to flush tlb. Fortunately,
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* mmu_spte_update() has already handled it perfectly.
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*
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* The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK:
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* - if we want to see if it has writable tlb entry or if the spte can be
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* writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most
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* case, otherwise
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* - if we fix page fault on the spte or do write-protection by dirty logging,
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* check PT_WRITABLE_MASK.
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*
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* TODO: introduce APIs to split these two cases.
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*/
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static inline int is_writable_pte(unsigned long pte)
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{
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return pte & PT_WRITABLE_MASK;
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}
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static inline bool is_write_protection(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
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}
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/*
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* Check if a given access (described through the I/D, W/R and U/S bits of a
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* page fault error code pfec) causes a permission fault with the given PTE
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* access rights (in ACC_* format).
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*
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* Return zero if the access does not fault; return the page fault error code
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* if the access faults.
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*/
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static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
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unsigned pte_access, unsigned pte_pkey,
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unsigned pfec)
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{
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int cpl = kvm_x86_ops->get_cpl(vcpu);
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unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
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/*
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* If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
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*
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* If CPL = 3, SMAP applies to all supervisor-mode data accesses
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* (these are implicit supervisor accesses) regardless of the value
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* of EFLAGS.AC.
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*
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* This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
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* the result in X86_EFLAGS_AC. We then insert it in place of
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* the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
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* but it will be one in index if SMAP checks are being overridden.
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* It is important to keep this branchless.
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*/
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unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
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int index = (pfec >> 1) +
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(smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
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bool fault = (mmu->permissions[index] >> pte_access) & 1;
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u32 errcode = PFERR_PRESENT_MASK;
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WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
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if (unlikely(mmu->pkru_mask)) {
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u32 pkru_bits, offset;
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/*
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* PKRU defines 32 bits, there are 16 domains and 2
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* attribute bits per domain in pkru. pte_pkey is the
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* index of the protection domain, so pte_pkey * 2 is
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* is the index of the first bit for the domain.
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*/
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pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
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/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
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offset = (pfec & ~1) +
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((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
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pkru_bits &= mmu->pkru_mask >> offset;
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errcode |= -pkru_bits & PFERR_PK_MASK;
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fault |= (pkru_bits != 0);
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}
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return -(u32)fault & errcode;
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}
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void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm);
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void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
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void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
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void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
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bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
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struct kvm_memory_slot *slot, u64 gfn);
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int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
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int kvm_mmu_post_init_vm(struct kvm *kvm);
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void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
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#endif
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