501 lines
14 KiB
C
Executable File
501 lines
14 KiB
C
Executable File
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/*
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Register offset and bit definition for SPI module
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Register offset and bit definition for SPI module.
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@file spi_reg.h
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2018. All rights reserved
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#ifndef _SPI_REG_H
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#define _SPI_REG_H
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#include <mach/rcw_macro.h>
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#define SPI_GYRO_OP_INTERVAL_MAX (0x1FFFFF)
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#define SPI_GYRO_TRANSFER_INTERVAL_MAX (0x1FFFFF)
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#define SPI_GYRO_TRANSFER_MIN (1)
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#define SPI_GYRO_TRANSFER_MAX (32)
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#define SPI_GYRO_TRSLEN_MIN (1)
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#define SPI_GYRO_TRSLEN_MAX (4)
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#define SPI_GYRO_OPLEN_MIN (1)
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#define SPI_GYRO_OPLEN_MAX (8)
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#define SPI_GYRO_FIFO_THRESHOLD (24)
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#define SPI_GYRO_FIFO_DEPTH (32) // Max depth = 32 OP
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#ifndef ENUM_DUMMY4WORD
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#define ENUM_DUMMY4WORD(m)
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#endif
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/*
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SPI_LATCHDELAY_ENUM
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*/
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typedef enum
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{
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SPI_LATCHDELAY_NORMAL, //< Normal latch
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SPI_LATCHDELAY_1T, //< Delay latch 1T
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SPI_LATCHDELAY_2T, //< Delay latch 2T
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ENUM_DUMMY4WORD(SPI_LATCHDELAY_ENUM)
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} SPI_LATCHDELAY_ENUM;
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/*
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SPI_PKT_LEN_ENUM
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*/
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typedef enum
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{
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SPI_PKT_LEN_ENUM_1BYTE, //< 1 byte
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SPI_PKT_LEN_ENUM_2BYTES, //< 2 byte
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ENUM_DUMMY4WORD(SPI_PKT_LEN_ENUM)
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} SPI_PKT_LEN_ENUM;
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/*
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SPI_PKT_CNT_ENUM
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*/
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typedef enum
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{
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SPI_PKT_CNT_ENUM_1PKT, //< 1 packet
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SPI_PKT_CNT_ENUM_2PKT, //< 2 packet
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SPI_PKT_CNT_ENUM_3PKT, //< 3 packet (reserved)
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SPI_PKT_CNT_ENUM_4PKT, //< 4 packet
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ENUM_DUMMY4WORD(SPI_PKT_CNT_ENUM)
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} SPI_PKT_CNT_ENUM;
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/*
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SPI_GYRO_MODE_ENUM
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*/
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typedef enum
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{
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SPI_GYRO_MODE_ENUM_SIETRIG, //< SIE VD trigger mode
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SPI_GYRO_MODE_ENUM_ONESHOT, //< f/w trigger one-shot mode
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SPI_GYRO_MODE_ENUM_FREERUN, //< f/w trigger free run mode
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ENUM_DUMMY4WORD(SPI_GYRO_MODE_ENUM)
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} SPI_GYRO_MODE_ENUM;
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/*
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SPI_CS_ACT_LVL_ENUM
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*/
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typedef enum
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{
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SPI_CS_ACT_LVL_LOW, //< low active
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SPI_CS_ACT_LVL_HIGH, //< high active
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ENUM_DUMMY4WORD(SPI_CS_ACT_LVL_ENUM)
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} SPI_CS_ACT_LVL_ENUM;
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#define SPI_CTRL_REG_OFS 0x00
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union SPI_CTRL_REG { /* SPI Control Register */
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uint32_t reg;
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struct {
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unsigned int spi_en:1; /* S/W must to take care this bit when disable SPI */
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unsigned int spics_value:1; /* Force the value of SPICS ,0:Force to low, 1:Force to high*/
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unsigned int spi_dma_en:1; /* Start DMA mode */
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unsigned int spi_dma_dis:1; /* Abort DMA mode */
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unsigned int spi_rdsts_en:1; /* Start read flash status */
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unsigned int spi_rdsts_dis:1; /* Abort read flash status */
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unsigned int spi_gyro_en:1; /* Start GYRO mode */
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unsigned int spi_gyro_dis:1; /* Abort GYRO mode */
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unsigned int reserved0:8;
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unsigned int spi_dma_sts:1; /* DMA mode status */
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unsigned int spi_rdsts_sts:1; /* Flash mode status */
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unsigned int spi_gyro_sts:1; /* Gyro mode status */
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unsigned int reserved1:13;
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} bit;
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};
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#define SPI_IO_REG_OFS 0x04
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union SPI_IO_REG { /* SPI IO Register */
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uint32_t reg;
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struct {
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unsigned int spi_gyro_cs_pol:1; /* CS polarity in Gyro mode */
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unsigned int reserved0:1;
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unsigned int spi_cpha:1; /* SPI_CPHA Setting clock phase */
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unsigned int spi_cpol:1; /* SPI_CPOL Setting clock polarity. */
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unsigned int reserved1:4;
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unsigned int spi_bus_width:2; /* SPI bus width */
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unsigned int reserved2:2;
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unsigned int spi_io_out_en:1; /* 0:SPI IO pins to input ,1:SPI IO pins to output */
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unsigned int spi_io_order:1; /* setup bit order of IO0 IO1 IO2 IO3 */
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unsigned int reserved3:2;
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unsigned int spi_auto_io_out_en:1; /* Set data pin to output mode when data is required to transmit */
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unsigned int reserved4:3;
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unsigned int spi_rdy_pol:1; /* Polarity of SPI_RDY */
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unsigned int reserved5:11;
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} bit;
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};
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#define SPI_CONFIG_REG_OFS 0x08
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union SPI_CONFIG_REG { /* SPI Configuration Register */
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uint32_t reg;
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struct {
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unsigned int spi_pkt_lsb_mode:1;/* LSb mode of each packet */
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unsigned int reserved0:1;
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unsigned int spi_pktlen:1; /* spi_pktlen. 0: 1 byte, 1: 2 bytes */
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unsigned int reserved1:1;
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unsigned int spi_pkt_cnt:2; /* packet count. 0: 1 pkt, 1: 2 pkt, , 2: 3 pkt, 3: 4 pkt */
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unsigned int spi_pkt_burst_handshake_en:1; /* Enable handshake for each packet burst */
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unsigned int reserved2:5;
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unsigned int spi_gyro_mode:2; /* 0: sie auto trig, 1: one-shot , 2: free run */
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unsigned int reserved3:2;
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unsigned int spi_pkt_burst_pre_cond:1; /* Packet burst pre-condition */
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unsigned int reserved4:1;
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unsigned int spi_pkt_burst_post_cond:1; /* Packet burst post-condition */
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unsigned int reserved5:13;
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} bit;
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};
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#define SPI_TIMING_REG_OFS 0x0C
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union SPI_TIMING_REG { /* SPI Timing Register */
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uint32_t reg;
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struct {
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unsigned int spi_cs_dly:8; /* delay count from SPI_CS asserted to SPI_CLK toggle */
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unsigned int reserved0:8;
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unsigned int spi_post_cond_dly:13; /* Packet burst post condition delay */
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unsigned int reserved1:3;
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} bit;
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};
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#define SPI_FLASH_CTRL_REG_OFS 0x10
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union SPI_FLASH_CTRL_REG { /* SPI Flash Control Register */
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uint32_t reg;
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struct {
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unsigned int spi_rdysts_bit:3; /* Flash ready bit position */
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unsigned int reserved0:5;
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unsigned int spi_rdysts_val:1; /* Flash ready value */
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unsigned int reserved1:7;
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unsigned int spi_rdsts_cmd:8; /* Command byte to get status of serial flash */
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unsigned int reserved2:8;
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} bit;
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};
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#define SPI_DLY_CHAIN_REG_OFS 0x14
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union SPI_DLY_CHAIN_REG { /* SPI Delay Chain Register */
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uint32_t reg;
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struct {
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unsigned int dly_clk_sel:6; /* delay how many delay cell to sample data */
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unsigned int reserved0:2;
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unsigned int dly_clk_polarity:1;
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unsigned int reserved1:1;
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unsigned int dly_clk_src:1;
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unsigned int reserved2:1;
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unsigned int latch_data_src:1;
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unsigned int reserved3:1;
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unsigned int dly_clk_edge:1;
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unsigned int reserved4:1;
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unsigned int latch_clk_shift:2;
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unsigned int reserved5:2;
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unsigned int latch_clk_edge:1;
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unsigned int reserved6:11;
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} bit;
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};
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#define SPI_STATUS_REG_OFS 0x18
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union SPI_STATUS_REG { /* SPI Status Register */
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uint32_t reg;
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struct {
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unsigned int spi_tdr_empty:1; /* Transmit data register empty. */
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unsigned int spi_rdr_full:1; /* Receive data register full. */
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unsigned int dma_abort_sts:1;
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unsigned int spi_dmaed:1; /* 0: DMA not transfer/receive end , 1: DMA transfer/receive end */
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unsigned int spi_rdstsed:1; /*0: SPI is reading status from serial flash or idle , 1: read SPI status done */
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unsigned int gyro_trs_rdy_sts:1;
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unsigned int gyro_overrun_sts:1;
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unsigned int all_gyrotrs_done_sts:1;
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unsigned int gyro_seq_err_sts:1;
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unsigned int gyro_trs_timeout_sts:1;
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unsigned int reserved0:22;
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} bit;
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};
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#define SPI_INTEN_REG_OFS 0x1C
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union SPI_INTEN_REG { /* SPI Status Register */
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uint32_t reg;
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struct {
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unsigned int spi_tdr_empty:1; /* Transmit data register empty. */
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unsigned int spi_rdr_full:1; /* Receive data register full. */
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unsigned int dma_abort_en:1;
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unsigned int spi_dmaed_en:1; /* 0: DMA not transfer/receive end , 1: DMA transfer/receive end */
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unsigned int spi_rdstsed_en:1; /* 0: SPI is reading status from serial flash or idle , 1: read SPI status done */
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unsigned int gyro_trs_rdy_en:1;
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unsigned int gyro_overrun_en:1;
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unsigned int all_gyrotrs_done_en:1;
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unsigned int gyro_seq_err_en:1;
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unsigned int gyro_trs_timeout_en:1;
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unsigned int reserved0:22;
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} bit;
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};
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#define SPI_RDR_REG_OFS 0x20
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union SPI_RDR_REG { /* SPI Receive Data Register */
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uint32_t reg;
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struct {
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unsigned int rdr:32; /* Receive data register */
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} bit;
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};
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#define SPI_TDR_REG_OFS 0x24
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union SPI_TDR_REG { /* SPI Transmit Data Register */
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uint32_t reg;
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struct {
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unsigned int tdr:32; /* Transmit data register */
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} bit;
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};
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/* 0x28, 0x2C: reserved */
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#define SPI_DMA_CTRL_REG_OFS 0x30
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union SPI_DMA_CTRL_REG { /* SPI DMA Control Register */
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uint32_t reg;
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struct {
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unsigned int dma_dir:1; /* 0: SPI2DMA, 1: DMA2SPI */
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unsigned int reserved0:31;
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} bit;
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};
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#define SPI_DMA_BUFSIZE_REG_OFS 0x34
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union SPI_DMA_BUFSIZE_REG { /* SPI DMA Control Register */
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uint32_t reg;
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struct {
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unsigned int spi_dma_bufsize:24; /* DMA buffer size register in byte alignment */
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unsigned int reserved0:8;
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} bit;
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};
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#define SPI_DMA_STARTADDR_REG_OFS 0x38
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union SPI_DMA_STARTADDR_REG { /* SPI DMA Control Register */
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uint32_t reg;
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struct {
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unsigned int spi_dma_start_addr:30; /* DMA DRAM starting address */
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unsigned int reserved0:2;
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} bit;
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};
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/* 0x3C: reserved */
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#define SPI_GYROSEN_CONFIG_REG_OFS 0x40
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union SPI_GYROSEN_CONFIG_REG { /* SPI Gyro sensor Configuration Register */
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uint32_t reg;
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struct {
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unsigned int trscnt:5; /* gyro transfer count per trigger */
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unsigned int reserved0:3;
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unsigned int trslen:2; /* gyro transfer length: how many OPs */
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unsigned int reserved1:6;
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unsigned int len_op0:3; /* OP0 byte length */
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unsigned int reserved2:1;
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unsigned int len_op1:3; /* OP1 byte length */
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unsigned int reserved3:1;
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unsigned int len_op2:3; /* OP2 byte length */
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unsigned int reserved4:1;
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unsigned int len_op3:3; /* OP3 byte length */
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unsigned int reserved5:1;
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} bit;
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};
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#define SPI_GYROSEN_OP_INTERVAL_REG_OFS 0x44
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union SPI_GYROSEN_OP_INTERVAL_REG { /* SPI Gyro sensor OP interval Register */
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uint32_t reg;
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struct {
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unsigned int op_interval:21;
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unsigned int reserved0:11;
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} bit;
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};
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#define SPI_GYROSEN_TRS_INTERVAL_REG_OFS 0x48
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union SPI_GYROSEN_TRS_INTERVAL_REG { /* SPI Gyro sensor Transfer interval Register */
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uint32_t reg;
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struct {
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unsigned int trs_interval:21;
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unsigned int reserved0:11;
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} bit;
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};
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#define SPI_GYROSEN_FIFO_STS_REG_OFS 0x4C
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union SPI_GYROSEN_FIFO_STS_REG { /* SPI Gyro sensor Transfer interval Register */
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uint32_t reg;
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struct {
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unsigned int valid_entry:6;
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unsigned int reserved0:26;
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} bit;
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};
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#define SPI_GYROSEN_TRS_STS_REG_OFS 0x50
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union SPI_GYROSEN_TRS_STS_REG { /* SPI Gyro Transfer Status Register */
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uint32_t reg;
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struct {
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unsigned int trsSts_0:1;
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unsigned int trsSts_1:1;
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unsigned int trsSts_2:1;
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unsigned int trsSts_3:1;
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unsigned int trsSts_4:1;
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unsigned int trsSts_5:1;
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unsigned int trsSts_6:1;
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unsigned int trsSts_7:1;
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unsigned int trsSts_8:1;
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unsigned int trsSts_9:1;
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unsigned int trsSts_10:1;
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unsigned int trsSts_11:1;
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unsigned int trsSts_12:1;
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unsigned int trsSts_13:1;
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unsigned int trsSts_14:1;
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unsigned int trsSts_15:1;
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unsigned int trsSts_16:1;
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unsigned int trsSts_17:1;
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unsigned int trsSts_18:1;
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unsigned int trsSts_19:1;
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unsigned int trsSts_20:1;
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unsigned int trsSts_21:1;
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unsigned int trsSts_22:1;
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unsigned int trsSts_23:1;
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unsigned int trsSts_24:1;
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unsigned int trsSts_25:1;
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unsigned int trsSts_26:1;
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unsigned int trsSts_27:1;
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unsigned int trsSts_28:1;
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unsigned int trsSts_29:1;
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unsigned int trsSts_30:1;
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unsigned int trsSts_31:1;
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} bit;
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};
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#define SPI_GYROSEN_TRS_INTEN_REG_OFS 0x54
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union SPI_GYROSEN_TRS_INTEN_REG { /* SPI Gyro Transfer Interrupt Enable Register */
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uint32_t reg;
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struct {
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unsigned int trsSts_0:1;
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unsigned int trsSts_1:1;
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unsigned int trsSts_2:1;
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unsigned int trsSts_3:1;
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unsigned int trsSts_4:1;
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unsigned int trsSts_5:1;
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unsigned int trsSts_6:1;
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unsigned int trsSts_7:1;
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unsigned int trsSts_8:1;
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unsigned int trsSts_9:1;
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unsigned int trsSts_10:1;
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unsigned int trsSts_11:1;
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unsigned int trsSts_12:1;
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unsigned int trsSts_13:1;
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unsigned int trsSts_14:1;
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unsigned int trsSts_15:1;
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unsigned int trsSts_16:1;
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unsigned int trsSts_17:1;
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unsigned int trsSts_18:1;
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unsigned int trsSts_19:1;
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unsigned int trsSts_20:1;
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unsigned int trsSts_21:1;
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unsigned int trsSts_22:1;
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unsigned int trsSts_23:1;
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unsigned int trsSts_24:1;
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unsigned int trsSts_25:1;
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unsigned int trsSts_26:1;
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unsigned int trsSts_27:1;
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unsigned int trsSts_28:1;
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unsigned int trsSts_29:1;
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unsigned int trsSts_30:1;
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unsigned int trsSts_31:1;
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} bit;
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};
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#define SPI_GYROSEN_COUNTER_REG_OFS 0x58
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union SPI_GYROSEN_COUNTER_REG { /* SPI Gyro sensor Transfer and OP Counter Register */
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uint32_t reg;
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struct {
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unsigned int transfer_counter:5;
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unsigned int reserved0:3;
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unsigned int op_counter:2;
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unsigned int reserved1:22;
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} bit;
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};
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#define SPI_GYROSEN_RX_DATA_REG_OFS 0x5C
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union SPI_GYROSEN_RX_DATA_REG { /* SPI Gyro sensor Receive Data Register */
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uint32_t reg;
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struct {
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unsigned int rxdata:32;
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} bit;
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};
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#define SPI_GYROSEN_TX_DATA1_REG_OFS 0x60
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union SPI_GYROSEN_TX_DATA1_REG { /* SPI Gyro sensor Transfer Data Register 1 */
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uint32_t reg;
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struct {
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unsigned int op0_lsb:32;
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} bit;
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};
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#define SPI_GYROSEN_TX_DATA2_REG_OFS 0x64
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union SPI_GYROSEN_TX_DATA2_REG { /* SPI Gyro sensor Transfer Data Register 2 */
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uint32_t reg;
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struct {
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unsigned int op0_msb:32;
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} bit;
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};
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/* 0x68, 0x6C: reserved */
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#define SPI_GYROSEN_TX_DATA3_REG_OFS 0x70
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union SPI_GYROSEN_TX_DATA3_REG { /* SPI Gyro sensor Transfer Data Register 3 */
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uint32_t reg;
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struct {
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unsigned int op1_lsb:32;
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} bit;
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};
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#define SPI_GYROSEN_TX_DATA4_REG_OFS 0x74
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union SPI_GYROSEN_TX_DATA4_REG { /* SPI Gyro sensor Transfer Data Register 4 */
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uint32_t reg;
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struct {
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unsigned int op1_msb:32;
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} bit;
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};
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/* 0x78, 0x7C: reserved */
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#define SPI_GYROSEN_TX_DATA5_REG_OFS 0x80
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union SPI_GYROSEN_TX_DATA5_REG { /* SPI Gyro sensor Transfer Data Register 5 */
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uint32_t reg;
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struct {
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unsigned int op2_lsb:32;
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} bit;
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};
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|
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#define SPI_GYROSEN_TX_DATA6_REG_OFS 0x84
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union SPI_GYROSEN_TX_DATA6_REG { /* SPI Gyro sensor Transfer Data Register 6 */
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uint32_t reg;
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|
struct {
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unsigned int op2_msb:32;
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|
} bit;
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|
};
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|
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/* 0x88, 0x8C: reserved */
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|
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#define SPI_GYROSEN_TX_DATA7_REG_OFS 0x90
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|
union SPI_GYROSEN_TX_DATA7_REG { /* SPI Gyro sensor Transfer Data Register 7 */
|
|
uint32_t reg;
|
|
struct {
|
|
unsigned int op3_lsb:32;
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|
} bit;
|
|
};
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|
|
|
#define SPI_GYROSEN_TX_DATA8_REG_OFS 0x94
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|
union SPI_GYROSEN_TX_DATA8_REG { /* SPI Gyro sensor Transfer Data Register 8 */
|
|
uint32_t reg;
|
|
struct {
|
|
unsigned int op3_msb:32;
|
|
} bit;
|
|
};
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|
#endif
|