235 lines
8.0 KiB
C
Executable File
235 lines
8.0 KiB
C
Executable File
/*
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* Faraday FTDMAC020 DMA controller
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*
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* Copyright (C) 2010 Faraday Technology
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* Copyright (C) 2010 Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __FTDMAC020_H
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#define __FTDMAC020_H
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#include <linux/dmaengine.h>
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#define FTDMAC020_OFFSET_ISR 0x0
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#define FTDMAC020_OFFSET_TCISR 0x4
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#define FTDMAC020_OFFSET_TCICR 0x8
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#define FTDMAC020_OFFSET_EAISR 0xc
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#define FTDMAC020_OFFSET_EAICR 0x10
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#define FTDMAC020_OFFSET_TCRAW 0x14
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#define FTDMAC020_OFFSET_EARAW 0x18
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#define FTDMAC020_OFFSET_CH_ENABLED 0x1c
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#define FTDMAC020_OFFSET_CH_BUSY 0x20
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#define FTDMAC020_OFFSET_CR 0x24
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#define FTDMAC020_OFFSET_SYNC 0x28
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#define FTDMAC020_OFFSET_REVISION 0x2c
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#define FTDMAC020_OFFSET_FEATURE 0x30
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#define FTDMAC020_OFFSET_CCR_CH(x) (0x100 + (x) * 0x20)
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#define FTDMAC020_OFFSET_CFG_CH(x) (0x104 + (x) * 0x20)
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#define FTDMAC020_OFFSET_SRC_CH(x) (0x108 + (x) * 0x20)
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#define FTDMAC020_OFFSET_DST_CH(x) (0x10c + (x) * 0x20)
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#define FTDMAC020_OFFSET_LLP_CH(x) (0x110 + (x) * 0x20)
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#define FTDMAC020_OFFSET_CYC_CH(x) (0x114 + (x) * 0x20)
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/*
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* Error/abort interrupt status/clear register
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* Error/abort status register
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*/
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#define FTDMAC020_EA_ERR_CH(x) (1 << (x))
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#define FTDMAC020_EA_ABT_CH(x) (1 << ((x) + 16))
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/*
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* Main configuration status register
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*/
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#define FTDMAC020_CR_ENABLE (1 << 0)
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#define FTDMAC020_CR_M0_BE (1 << 1) /* master 0 big endian */
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#define FTDMAC020_CR_M1_BE (1 << 2) /* master 1 big endian */
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/*
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* Channel control register
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*/
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#define FTDMAC020_CCR_ENABLE (1 << 0)
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#define FTDMAC020_CCR_DST_M1 (1 << 1)
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#define FTDMAC020_CCR_SRC_M1 (1 << 2)
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#define FTDMAC020_CCR_DST_INC (0x0 << 3)
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#define FTDMAC020_CCR_DST_DEC (0x1 << 3)
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#define FTDMAC020_CCR_DST_FIXED (0x2 << 3)
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#define FTDMAC020_CCR_SRC_INC (0x0 << 5)
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#define FTDMAC020_CCR_SRC_DEC (0x1 << 5)
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#define FTDMAC020_CCR_SRC_FIXED (0x2 << 5)
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#define FTDMAC020_CCR_HANDSHAKE (1 << 7)
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#define FTDMAC020_CCR_DST_WIDTH_8 (0x0 << 8)
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#define FTDMAC020_CCR_DST_WIDTH_16 (0x1 << 8)
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#define FTDMAC020_CCR_DST_WIDTH_32 (0x2 << 8)
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#define FTDMAC020_CCR_DST_WIDTH_64 (0x3 << 8)
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#define FTDMAC020_CCR_SRC_WIDTH_8 (0x0 << 11)
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#define FTDMAC020_CCR_SRC_WIDTH_16 (0x1 << 11)
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#define FTDMAC020_CCR_SRC_WIDTH_32 (0x2 << 11)
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#define FTDMAC020_CCR_SRC_WIDTH_64 (0x3 << 11)
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#define FTDMAC020_CCR_ABORT (1 << 15)
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#define FTDMAC020_CCR_BURST_1 (0x0 << 16)
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#define FTDMAC020_CCR_BURST_4 (0x1 << 16)
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#define FTDMAC020_CCR_BURST_8 (0x2 << 16)
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#define FTDMAC020_CCR_BURST_16 (0x3 << 16)
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#define FTDMAC020_CCR_BURST_32 (0x4 << 16)
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#define FTDMAC020_CCR_BURST_64 (0x5 << 16)
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#define FTDMAC020_CCR_BURST_128 (0x6 << 16)
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#define FTDMAC020_CCR_BURST_256 (0x7 << 16)
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#define FTDMAC020_CCR_PRIVILEGED (1 << 19)
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#define FTDMAC020_CCR_BUFFERABLE (1 << 20)
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#define FTDMAC020_CCR_CACHEABLE (1 << 21)
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#define FTDMAC020_CCR_PRIO_0 (0x0 << 22)
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#define FTDMAC020_CCR_PRIO_1 (0x1 << 22)
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#define FTDMAC020_CCR_PRIO_2 (0x2 << 22)
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#define FTDMAC020_CCR_PRIO_3 (0x3 << 22)
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#define FTDMAC020_CCR_FIFOTH_1 (0x0 << 24)
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#define FTDMAC020_CCR_FIFOTH_2 (0x1 << 24)
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#define FTDMAC020_CCR_FIFOTH_4 (0x2 << 24)
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#define FTDMAC020_CCR_FIFOTH_8 (0x3 << 24)
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#define FTDMAC020_CCR_FIFOTH_16 (0x4 << 24)
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#define FTDMAC020_CCR_MASK_TC (1 << 31)
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/*
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* Channel configuration register
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*/
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#define FTDMAC020_CFG_MASK_TCI (1 << 0) /* mask tc interrupt */
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#define FTDMAC020_CFG_MASK_EI (1 << 1) /* mask error interrupt */
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#define FTDMAC020_CFG_MASK_AI (1 << 2) /* mask abort interrupt */
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#define FTDMAC020_CFG_SRC_HANDSHAKE(x) (((x) & 0xf) << 3)
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#define FTDMAC020_CFG_SRC_HANDSHAKE_EN (1 << 7)
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#define FTDMAC020_CFG_BUSY (1 << 8)
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#define FTDMAC020_CFG_DST_HANDSHAKE(x) (((x) & 0xf) << 9)
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#define FTDMAC020_CFG_DST_HANDSHAKE_EN (1 << 13)
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#define FTDMAC020_CFG_LLP_CNT(cfg) (((cfg) >> 16) & 0xf)
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/*
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* Link list descriptor pointer
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*/
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#define FTDMAC020_LLP_M1 (1 << 0)
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#define FTDMAC020_LLP_ADDR(a) ((a) & ~0x3)
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/*
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* Transfer size register
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*/
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#define FTDMAC020_CYC_MASK 0x3fffff
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/**
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* Table 3-1. Address Map for Linked List Descriptor(Base Address: Cn_LLP[31:2])
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*
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* struct ftdmac020_lld - hardware link list descriptor.
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* @src: source physical address
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* @dst: destination physical addr
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* @next: phsical address to the next link list descriptor
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* @ctrl: control field
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* @cycle: transfer size
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*
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* should be word aligned.
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*/
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struct ftdmac020_lld {
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dma_addr_t src; /* SrcAddr */
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dma_addr_t dst; /* DstAddr */
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dma_addr_t next; /* LLP */
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unsigned int ctrl; /* Control */
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unsigned int cycle; /* Total Size */
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};
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#define FTDMAC020_LLD_CTRL_DST_M1 (1 << 16)
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#define FTDMAC020_LLD_CTRL_SRC_M1 (1 << 17)
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#define FTDMAC020_LLD_CTRL_DST_INC (0x0 << 18)
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#define FTDMAC020_LLD_CTRL_DST_DEC (0x1 << 18)
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#define FTDMAC020_LLD_CTRL_DST_FIXED (0x2 << 18)
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#define FTDMAC020_LLD_CTRL_SRC_INC (0x0 << 20)
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#define FTDMAC020_LLD_CTRL_SRC_DEC (0x1 << 20)
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#define FTDMAC020_LLD_CTRL_SRC_FIXED (0x2 << 20)
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#define FTDMAC020_LLD_CTRL_DST_WIDTH_8 (0x0 << 22)
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#define FTDMAC020_LLD_CTRL_DST_WIDTH_16 (0x1 << 22)
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#define FTDMAC020_LLD_CTRL_DST_WIDTH_32 (0x2 << 22)
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#define FTDMAC020_LLD_CTRL_DST_WIDTH_64 (0x3 << 22)
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#define FTDMAC020_LLD_CTRL_SRC_WIDTH_8 (0x0 << 25)
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#define FTDMAC020_LLD_CTRL_SRC_WIDTH_16 (0x1 << 25)
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#define FTDMAC020_LLD_CTRL_SRC_WIDTH_32 (0x2 << 25)
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#define FTDMAC020_LLD_CTRL_SRC_WIDTH_64 (0x3 << 25)
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#define FTDMAC020_LLD_CTRL_MASK_TC (1 << 28)
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#define FTDMAC020_LLD_CTRL_FIFOTH_1 (0x0 << 29)
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#define FTDMAC020_LLD_CTRL_FIFOTH_2 (0x1 << 29)
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#define FTDMAC020_LLD_CTRL_FIFOTH_4 (0x2 << 29)
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#define FTDMAC020_LLD_CTRL_FIFOTH_8 (0x3 << 29)
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#define FTDMAC020_LLD_CTRL_FIFOTH_16 (0x4 << 29)
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#define FTDMAC020_LLD_CYCLE_MASK 0x3fffff
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enum ftdmac020_channels {
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FTDMAC020_CHANNEL_0 = (1 << 0),
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FTDMAC020_CHANNEL_1 = (1 << 1),
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FTDMAC020_CHANNEL_2 = (1 << 2),
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FTDMAC020_CHANNEL_3 = (1 << 3),
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FTDMAC020_CHANNEL_4 = (1 << 4),
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FTDMAC020_CHANNEL_5 = (1 << 5),
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FTDMAC020_CHANNEL_6 = (1 << 6),
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FTDMAC020_CHANNEL_7 = (1 << 7),
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FTDMAC020_CHANNEL_ALL = 0xff,
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};
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enum ftdmac020_burst {
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FTDMAC020_BURST_SZ_1 = 0,
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FTDMAC020_BURST_SZ_4,
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FTDMAC020_BURST_SZ_8,
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FTDMAC020_BURST_SZ_16,
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FTDMAC020_BURST_SZ_32,
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FTDMAC020_BURST_SZ_64,
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FTDMAC020_BURST_SZ_128,
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FTDMAC020_BURST_SZ_256
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};
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enum ftdmac020_ahbmaster {
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FTDMA020_AHBMASTER_0 = 0,
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FTDMA020_AHBMASTER_1
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};
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/**
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* struct ftdmac020_dma_slave - DMA slave data
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* @common: physical address and register width...
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* @id: specify which ftdmac020 device to use, -1 for wildcard
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* @handshake: hardware handshake number, -1 to disable handshake mode
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*/
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struct ftdmac020_dma_slave {
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struct dma_slave_config common;
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int id;
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int handshake; /* handshake number, -1 means disable */
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enum ftdmac020_burst src_size; /* source burst size selection */
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enum ftdmac020_ahbmaster src_sel; /* AHB Master selection */
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enum ftdmac020_ahbmaster dst_sel; /* AHB Master selection */
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};
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/**
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* ftdmac020_chan_filter() - filter function for dma_request_channel().
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* @chan: DMA channel
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* @data: pointer to ftdmac020_dma_slave
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*/
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bool ftdmac020_chan_filter(struct dma_chan *chan, void *data);
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/**
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* ftdmac020_set_platform_chanfilter() - filter function for platform dependent.
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* @chan_id: DMA channel
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* @chan_filter_fn: filter function used in platform. When ftdmac020_chan_filter is called, it will
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* call chan_filter_fn as well.
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* @return value: 0 for success, -1 for fail
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*/
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int ftdmac020_set_platform_chanfilter(int (*chan_filter_fn)(int chan_id));
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#endif /* __FTDMAC020_H */
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