328 lines
14 KiB
C
Executable File
328 lines
14 KiB
C
Executable File
/*
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* driver/mmc/nvt_ivot_mmc.h
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*
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* Author: Howard Chang
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* Created: April 8, 2016
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* Copyright: Novatek Inc.
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*
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*/
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#ifndef __NVT_IVOT_MMC_H__
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#define __NVT_IVOT_MMC_H__
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#include "nvt_ivot_mmcreg.h"
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int nvt_mmc_init(int id);
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#define CLK_26M (26000000)
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#define CLK_52M (52000000)
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#define CLK_200M (200000000)
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#define CLK_100M (100000000)
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#if (defined(CONFIG_TARGET_NA51090_A64) || defined(CONFIG_TARGET_NA51102_A64) || defined(CONFIG_TARGET_NA51103_A64))
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#define PIN_SDIO_CFG_1ST_PINMUX 0x02
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#define PIN_SDIO2_CFG_1ST_PINMUX 0x10
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#define PIN_SDIO2_CFG_BUS_WIDTH 0x20
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#define PIN_SDIO2_CFG_DS 0x40
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#else
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#define PIN_SDIO_CFG_8BITS 0x02 /*8 bits wide*/
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#define PIN_SDIO_CFG_2ND_PINMUX 0x10 /*2nd pinmux location*/
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#define PIN_SDIO_CFG_3RD_PINMUX 0x20 /*3rd pinmux location*/
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#endif
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#define BIT(nr) (1UL << (nr))
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#if (defined(CONFIG_TARGET_NA51090_A64) || defined(CONFIG_TARGET_NA51102_A64) || defined(CONFIG_TARGET_NA51103_A64))
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#define PAD_PUPD0_REG_OFS 0x00
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#define PAD_REG_TO_BASE(reg) (((reg)/(4))*(32))
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#define PAD_DS_CGPIO_BASE PAD_REG_TO_BASE(0x50) // 0x50~0x54
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#define PAD_DS_PGPIO_BASE PAD_REG_TO_BASE(0x60) // 0x60~0x74
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#define PAD_DS_CGPIO2 (PAD_DS_CGPIO_BASE + 8) ///< C_GPIO_2
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#define PAD_DS_CGPIO3 (PAD_DS_CGPIO_BASE + 12) ///< C_GPIO_3
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#define PAD_DS_CGPIO4 (PAD_DS_CGPIO_BASE + 16) ///< C_GPIO_4
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#define PAD_DS_CGPIO5 (PAD_DS_CGPIO_BASE + 20) ///< C_GPIO_5
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#define PAD_DS_CGPIO8 (PAD_DS_CGPIO_BASE + 32) ///< C_GPIO_8
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#define PAD_DS_CGPIO9 (PAD_DS_CGPIO_BASE + 36) ///< C_GPIO_9
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#define PAD_DS_CGPIO10 (PAD_DS_CGPIO_BASE + 40) ///< C_GPIO_10
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#define PAD_DS_CGPIO11 (PAD_DS_CGPIO_BASE + 44) ///< C_GPIO_11
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#define PAD_DS_CGPIO12 (PAD_DS_CGPIO_BASE + 48) ///< C_GPIO_12
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#define PAD_DS_CGPIO13 (PAD_DS_CGPIO_BASE + 52) ///< C_GPIO_13
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#define PAD_DS_PGPIO12 (PAD_DS_PGPIO_BASE + 48) ///< P_GPIO_12
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#define PAD_DS_PGPIO13 (PAD_DS_PGPIO_BASE + 52) ///< P_GPIO_13
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#define PAD_DS_PGPIO15 (PAD_DS_PGPIO_BASE + 60) ///< P_GPIO_15
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#define PAD_DS_PGPIO16 (PAD_DS_PGPIO_BASE + 64) ///< P_GPIO_16
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#define PAD_DS_PGPIO17 (PAD_DS_PGPIO_BASE + 68) ///< P_GPIO_17
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#define PAD_DS_PGPIO18 (PAD_DS_PGPIO_BASE + 72) ///< P_GPIO_18
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#else
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#define PAD_PUPD0_REG_OFS 0x00
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#define PAD_PUPD1_REG_OFS 0x04
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#define PAD_PUPD2_REG_OFS 0x08
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#define PAD_PUPD3_REG_OFS 0x0C
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#define PAD_PUPD4_REG_OFS 0x10
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#define PAD_PUPD5_REG_OFS 0x14
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#define PAD_PUPD6_REG_OFS 0x18
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#define PAD_PUPD7_REG_OFS 0x1C
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#define PAD_PUPD8_REG_OFS 0x20
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#define PAD_PUPD9_REG_OFS 0x24
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#define PAD_DS_REG_OFS 0x40
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#define PAD_DS1_REG_OFS 0x44
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#define PAD_DS2_REG_OFS 0x48
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#define PAD_DS3_REG_OFS 0x4C
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#define PAD_DS4_REG_OFS 0x50
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#define PAD_DS5_REG_OFS 0x54
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#define PAD_DS6_REG_OFS 0x58
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#define PAD_DS7_REG_OFS 0x5C
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#define PAD_DS8_REG_OFS 0x60
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#define PAD_DS9_REG_OFS 0x64
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#define PAD_DS10_REG_OFS 0x68
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#define PAD_DS11_REG_OFS 0x90
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#define PAD_DS_GPIO_BASE_MASK 0xFFFF
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#define PAD_DS_GROUP_10_MSK 0x0003
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#define PAD_DS_GROUP_16_MSK 0x0030
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#define PAD_DS_GROUP_40_MSK 0xFF00
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#define PAD_DS_GROUP_COMBO_MSK 0xFFFFF
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#define PAD_DS_CGPIO_BASE 0
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#define PAD_DS_HGPIO_BASE 320
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#define PAD_DS_GROUP_10 0x00000000
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#define PAD_DS_GROUP_16 0x10000000
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#define PAD_DS_GROUP_40 0x80000000
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#define PAD_DS_GROUP_MASK 0xF0000000
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#ifdef CONFIG_TARGET_NA51089
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#define PAD_DS_CGPIO0 ((PAD_DS_CGPIO_BASE + 0) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO1 ((PAD_DS_CGPIO_BASE + 2) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO2 ((PAD_DS_CGPIO_BASE + 4) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO3 ((PAD_DS_CGPIO_BASE + 6) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO4 ((PAD_DS_CGPIO_BASE + 8) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO5 ((PAD_DS_CGPIO_BASE + 10) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO6 ((PAD_DS_CGPIO_BASE + 12) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO7 ((PAD_DS_CGPIO_BASE + 14) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO8 ((PAD_DS_CGPIO_BASE + 16) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO9 ((PAD_DS_CGPIO_BASE + 18) | PAD_DS_GROUP_16)
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#else
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#define PAD_DS_CGPIO0 ((PAD_DS_CGPIO_BASE + 0) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO1 ((PAD_DS_CGPIO_BASE + 2) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO2 ((PAD_DS_CGPIO_BASE + 4) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO3 ((PAD_DS_CGPIO_BASE + 6) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO4 ((PAD_DS_CGPIO_BASE + 8) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO5 ((PAD_DS_CGPIO_BASE + 10) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO6 ((PAD_DS_CGPIO_BASE + 12) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO7 ((PAD_DS_CGPIO_BASE + 14) | PAD_DS_GROUP_10)
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#define PAD_DS_CGPIO8 ((PAD_DS_CGPIO_BASE + 16) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO9 ((PAD_DS_CGPIO_BASE + 18) | PAD_DS_GROUP_10)
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#endif
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#define PAD_DS_CGPIO11 ((PAD_DS_CGPIO_BASE + 0) | PAD_DS_GROUP_40)
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#define PAD_DS_CGPIO12 ((PAD_DS_CGPIO_BASE + 4) | PAD_DS_GROUP_40)
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#define PAD_DS_CGPIO13 ((PAD_DS_CGPIO_BASE + 8) | PAD_DS_GROUP_40)
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#define PAD_DS_CGPIO14 ((PAD_DS_CGPIO_BASE + 12) | PAD_DS_GROUP_40)
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#define PAD_DS_CGPIO15 ((PAD_DS_CGPIO_BASE + 16) | PAD_DS_GROUP_40)
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#define PAD_DS_CGPIO16 ((PAD_DS_CGPIO_BASE + 20) | PAD_DS_GROUP_40)
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#define PAD_DS_CGPIO17 ((PAD_DS_CGPIO_BASE + 24) | PAD_DS_GROUP_40)
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#define PAD_DS_CGPIO18 ((PAD_DS_CGPIO_BASE + 36) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO19 ((PAD_DS_CGPIO_BASE + 38) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO20 ((PAD_DS_CGPIO_BASE + 40) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO21 ((PAD_DS_CGPIO_BASE + 42) | PAD_DS_GROUP_16)
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#define PAD_DS_CGPIO22 ((PAD_DS_CGPIO_BASE + 44) | PAD_DS_GROUP_16)
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#define PAD_DS_HSIGPIO0 ((PAD_DS_HGPIO_BASE + 0) | PAD_DS_GROUP_10)
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#define PAD_DRIVINGSINK_4MA 0x0001 ///< Pad driver/sink 4mA
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#define PAD_DRIVINGSINK_10MA 0x0202 ///< Pad driver/sink 10mA
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#define PAD_DRIVINGSINK_6MA 0x0010 ///< Pad driver/sink 6mA
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#define PAD_DRIVINGSINK_16MA 0x0020 ///< Pad driver/sink 16mA
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#define PAD_DRIVINGSINK_5MA 0x0100 ///< Pad driver/sink 5mA
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#define PAD_DRIVINGSINK_15MA 0x0400 ///< Pad driver/sink 15mA
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#define PAD_DRIVINGSINK_20MA 0x0800 ///< Pad driver/sink 20mA
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#define PAD_DRIVINGSINK_25MA 0x1000 ///< Pad driver/sink 25mA
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#define PAD_DRIVINGSINK_30MA 0x2000 ///< Pad driver/sink 30mA
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#define PAD_DRIVINGSINK_35MA 0x4000 ///< Pad driver/sink 35mA
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#define PAD_DRIVINGSINK_40MA 0x8000 ///< Pad driver/sink 40mA
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#define PAD_DRIVINGSINK_8MA 0x10000 ///< Pad driver/sink 8mA
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#define PAD_DRIVINGSINK_12MA 0x20000 ///< Pad driver/sink 12mA
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#endif
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#define SDIO_HOST_WRITE_DATA (FALSE)
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#define SDIO_HOST_READ_DATA (TRUE)
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enum SDIO_MODE_DRIVING {
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SDIO_DS_MODE_CLK = 0,
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SDIO_DS_MODE_CMD,
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SDIO_DS_MODE_DATA,
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SDIO_HS_MODE_CLK,
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SDIO_HS_MODE_CMD,
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SDIO_HS_MODE_DATA,
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SDIO_SDR50_MODE_CLK,
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SDIO_SDR50_MODE_CMD,
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SDIO_SDR50_MODE_DATA,
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SDIO_SDR104_MODE_CLK,
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SDIO_SDR104_MODE_CMD,
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SDIO_SDR104_MODE_DATA,
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SDIO_MAX_MODE_DRIVING,
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};
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struct mmc_nvt_host {
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struct mmc_cmd *cmd;
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struct mmc_data *data;
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u32 mmc_input_clk;
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u32 mmc_default_clk;
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void __iomem *base;
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struct resource *mem_res;
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int id;
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unsigned char bus_mode;
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unsigned char data_dir;
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unsigned char suspended;
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/* buffer is used during PIO of one scatterlist segment, and
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* is updated along with buffer_bytes_left. bytes_left applies
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* to all N blocks of the PIO transfer.
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*/
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u8 *buffer;
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u32 buffer_bytes_left;
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u32 bytes_left;
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bool do_dma;
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/*early data*/
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bool data_early;
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u32 pad_driving[SDIO_MAX_MODE_DRIVING];
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u32 pinmux_value;
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int enable_8bits;
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u32 ext_caps;
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/* Version of the MMC/SD controller */
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u8 version;
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/* for ns in one cycle calculation */
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unsigned ns_in_one_cycle;
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int indly_sel;
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};
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/*
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SDIO send command execution result.
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Encoding of sdiohost_sendcmd() result.
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*/
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#define SDIO_HOST_CMD_OK (0) /* command execution OK*/
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#define SDIO_HOST_RSP_TIMEOUT (-1) /* response timeout*/
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#define SDIO_HOST_RSP_CRCFAIL (-2) /* response CRC fail*/
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#define SDIO_HOST_CMD_FAIL (-3) /* command fail*/
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/*
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SDIO data transfer result.
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Encoding of sdiohost_waitdataend() result.
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*/
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#define SDIO_HOST_DATA_OK (0) /* data transfer OK*/
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#define SDIO_HOST_DATA_TIMEOUT (-1) /* data block timeout*/
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#define SDIO_HOST_DATA_CRCFAIL (-2) /* data block CRC fail*/
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#define SDIO_HOST_DATA_FAIL (-3) /* data transfer fail*/
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#define SDIO_HOST_BOOT_ACK_OK (0)
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#define SDIO_HOST_BOOT_ACK_TIMEOUT (-1)
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#define SDIO_HOST_BOOT_ACK_ERROR (-2)
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#define SDIO_HOST_BOOT_END (0)
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#define SDIO_HOST_BOOT_END_ERROR (-1)
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/*
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SDIO response type
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@note for sdiohost_sendcmd()
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*/
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typedef enum {
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SDIO_HOST_RSP_NONE, /* No response*/
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SDIO_HOST_RSP_SHORT, /* Short response*/
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SDIO_HOST_RSP_LONG, /* Long response*/
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SDIO_HOST_RSP_SHORT_TYPE2, /* Short response timeout is 5 bus clock*/
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SDIO_HOST_RSP_LONG_TYPE2, /* Long response timeout is 5 bus clock*/
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SDIO_HOST_RSP_VOLT_DETECT, /* voltage detect response*/
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ENUM_DUMMY4WORD(SDIO_HOST_RESPONSE)
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} SDIO_HOST_RESPONSE;
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#define SDIO_HOST_MAX_VOLT_TIMER (0xFFF) /* max value of voltage switch timer*/
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#define SDIO_DES_TABLE_NUM (128)
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#define SDIO_DES_WORD_SIZE (3) /*descriptor 3 word*/
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#define SDIO_HOST_MAX_DATA_LENGTH (64*1024*1024)
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#if (defined(CONFIG_TARGET_NA51090) || defined(CONFIG_TARGET_NA51090_A64) || defined(CONFIG_TARGET_NA51102) || defined(CONFIG_TARGET_NA51102_A64) || defined(CONFIG_TARGET_NA51103) || defined(CONFIG_TARGET_NA51103_A64))
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#define SDIO_HOST_DATA_FIFO_DEPTH (32)
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#else
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#define SDIO_HOST_DATA_FIFO_DEPTH (16)
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#endif
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/*sdio_protocol.h*/
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#define SDIO_HOST_WRITE_DATA (FALSE)
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#define SDIO_HOST_READ_DATA (TRUE)
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/* Command Register Bit*/
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#define SDIO_CMD_REG_INDEX 0x0000003F /* bit 5..0*/
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#define SDIO_CMD_REG_NEED_RSP 0x00000040 /* bit 6*/
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#define SDIO_CMD_REG_LONG_RSP 0x000000C0 /* bit 7*/
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#define SDIO_CMD_REG_RSP_TYPE2 0x00000100 /* bit 8*/
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#define SDIO_CMD_REG_APP_CMD 0x00000000 /* bit x*/
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#define SDIO_CMD_REG_ABORT 0x00000800 /* bit 11*/
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#define SDIO_CMD_REG_VOLTAGE_SWITCH_DETECT 0x00001000 /* bit 12*/
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/* Status/Interrupt Mask Register Bit*/
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#define SDIO_STATUS_REG_RSP_CRC_FAIL 0x00000001 /* bit 0*/
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#define SDIO_STATUS_REG_DATA_CRC_FAIL 0x00000002 /* bit 1*/
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#define SDIO_STATUS_REG_RSP_TIMEOUT 0x00000004 /* bit 2*/
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#define SDIO_STATUS_REG_DATA_TIMEOUT 0x00000008 /* bit 3*/
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#define SDIO_STATUS_REG_RSP_CRC_OK 0x00000010 /* bit 4*/
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#define SDIO_STATUS_REG_DATA_CRC_OK 0x00000020 /* bit 5*/
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#define SDIO_STATUS_REG_CMD_SEND 0x00000040 /* bit 6*/
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#define SDIO_STATUS_REG_DATA_END 0x00000080 /* bit 7*/
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#define SDIO_STATUS_REG_INT 0x00000100 /* bit 8*/
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#define SDIO_STATUS_REG_READWAIT 0x00000200 /* bit 9*/
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#define SDIO_STATUS_REG_EMMC_BOOTACKREV 0x00008000 /* bit 15*/
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#define SDIO_STATUS_REG_EMMC_BOOTACKTOUT 0x00010000 /* bit 16*/
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#define SDIO_STATUS_REG_EMMC_BOOTEND 0x00020000 /* bit 17*/
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#define SDIO_STATUS_REG_EMMC_BOOTACKERR 0x00040000 /* bit 18*/
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#define SDIO_STATUS_REG_DMA_ERR 0x00080000 /* bit 19*/
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#define SDIO_INTMASK_ALL 0x000003FF /* bit 9..0*/
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/* Bus Width Register bit definition*/
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#define SDIO_BUS_WIDTH1 0x0 /* bit 1..0*/
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#define SDIO_BUS_WIDTH4 0x1 /* bit 1..0*/
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#define SDIO_BUS_WIDTH8 0x2 /* bit 1..0*/
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#define MMCST_RSP_CRC_FAIL BIT(0)
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#define MMCST_DATA_CRC_FAIL BIT(1)
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#define MMCST_RSP_TIMEOUT BIT(2)
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#define MMCST_DATA_TIMEOUT BIT(3)
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#define MMCST_RSP_CRC_OK BIT(4)
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#define MMCST_DATA_CRC_OK BIT(5)
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#define MMCST_CMD_SENT BIT(6)
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#define MMCST_DATA_END BIT(7)
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#define MMCST_SDIO_INT BIT(8)
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#define MMCST_READ_WAIT BIT(9)
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#define MMCST_CARD_BUSY2READY BIT(10)
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#define MMCST_VOL_SWITCH_END BIT(11)
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#define MMCST_VOL_SWITCH_TIMEOUT BIT(12)
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#define MMCST_RSP_VOL_SWITCH_FAIL BIT(13)
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#define MMCST_VOL_SWITCH_GLITCH BIT(14)
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#define MMCST_EMMC_BOOT_ACK_RECEIVE BIT(15)
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#define MMCST_EMMC_BOOT_ACK_TIMEOUT BIT(16)
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#define MMCST_EMMC_BOOT_END BIT(17)
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#define MMCST_EMMC_BOOT_ACK_ERROR BIT(18)
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#define MMCST_DMA_ERROR BIT(19)
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#define SDIO_HOST_ID_1 0
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#define SDIO_HOST_ID_2 1
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#define SDIO_HOST_ID_3 2
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typedef enum {
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SDIO_MODE_DS = 25000000,
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SDIO_MODE_HS = 50000000,
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SDIO_MODE_SDR50 = 100000000,
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SDIO_MODE_SDR104 = 208000000,
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ENUM_DUMMY4WORD(SDIO_SPEED_MODE)
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} SDIO_SPEED_MODE;
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#endif
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