297 lines
7.8 KiB
C
Executable File
297 lines
7.8 KiB
C
Executable File
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDMRAINFO_H__
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#define __PHYDMRAINFO_H__
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#define RAINFO_VERSION "8.0"
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#define FORCED_UPDATE_RAMASK_PERIOD 5
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#define H2C_MAX_LENGTH 7
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#define RA_FLOOR_UP_GAP 3
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#define RA_FLOOR_TABLE_SIZE 7
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#define ACTIVE_TP_THRESHOLD 1
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#define RA_RETRY_DESCEND_NUM 2
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#define RA_RETRY_LIMIT_LOW 4
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#define RA_RETRY_LIMIT_HIGH 32
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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#define FIRST_MACID 1
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#else
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#define FIRST_MACID 0
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#endif
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/* @1 ============================================================
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* 1 enumrate
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* 1 ============================================================
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*/
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enum phydm_ra_dbg_para {
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RADBG_PCR_TH_OFFSET = 0,
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RADBG_RTY_PENALTY = 1,
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RADBG_N_HIGH = 2,
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RADBG_N_LOW = 3,
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RADBG_TRATE_UP_TABLE = 4,
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RADBG_TRATE_DOWN_TABLE = 5,
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RADBG_TRYING_NECESSARY = 6,
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RADBG_TDROPING_NECESSARY = 7,
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RADBG_RATE_UP_RTY_RATIO = 8,
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RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
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RADBG_DEBUG_MONITOR1 = 0xc,
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RADBG_DEBUG_MONITOR2 = 0xd,
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RADBG_DEBUG_MONITOR3 = 0xe,
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RADBG_DEBUG_MONITOR4 = 0xf,
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RADBG_DEBUG_MONITOR5 = 0x10,
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NUM_RA_PARA
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};
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enum phydm_wireless_mode {
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PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
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PHYDM_WIRELESS_MODE_A = 0x01,
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PHYDM_WIRELESS_MODE_B = 0x02,
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PHYDM_WIRELESS_MODE_G = 0x04,
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PHYDM_WIRELESS_MODE_AUTO = 0x08,
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PHYDM_WIRELESS_MODE_N_24G = 0x10,
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PHYDM_WIRELESS_MODE_N_5G = 0x20,
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PHYDM_WIRELESS_MODE_AC_5G = 0x40,
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PHYDM_WIRELESS_MODE_AC_24G = 0x80,
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PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
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PHYDM_WIRELESS_MODE_MAX = 0x800,
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PHYDM_WIRELESS_MODE_ALL = 0xFFFF
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};
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enum phydm_rateid_idx {
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PHYDM_BGN_40M_2SS = 0,
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PHYDM_BGN_40M_1SS = 1,
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PHYDM_BGN_20M_2SS = 2,
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PHYDM_BGN_20M_1SS = 3,
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PHYDM_GN_N2SS = 4,
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PHYDM_GN_N1SS = 5,
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PHYDM_BG = 6,
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PHYDM_G = 7,
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PHYDM_B_20M = 8,
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PHYDM_ARFR0_AC_2SS = 9,
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PHYDM_ARFR1_AC_1SS = 10,
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PHYDM_ARFR2_AC_2G_1SS = 11,
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PHYDM_ARFR3_AC_2G_2SS = 12,
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PHYDM_ARFR4_AC_3SS = 13,
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PHYDM_ARFR5_N_3SS = 14,
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PHYDM_ARFR7_N_4SS = 15,
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PHYDM_ARFR6_AC_4SS = 16
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};
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enum phydm_qam_order {
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PHYDM_QAM_CCK = 0,
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PHYDM_QAM_BPSK = 1,
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PHYDM_QAM_QPSK = 2,
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PHYDM_QAM_16QAM = 3,
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PHYDM_QAM_64QAM = 4,
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PHYDM_QAM_256QAM = 5
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};
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#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */
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struct _phydm_txstatistic_ {
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u32 hw_total_tx;
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u32 hw_tx_success;
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u32 hw_tx_rty;
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u32 hw_tx_drop;
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};
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/* @1 ============================================================
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* 1 structure
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* 1 ============================================================
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*/
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struct _odm_ra_info_ {
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u8 rate_id;
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u32 rate_mask;
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u32 ra_use_rate;
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u8 rate_sgi;
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u8 rssi_sta_ra;
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u8 pre_rssi_sta_ra;
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u8 sgi_enable;
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u8 decision_rate;
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u8 pre_rate;
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u8 highest_rate;
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u8 lowest_rate;
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u32 nsc_up;
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u32 nsc_down;
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u16 RTY[5];
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u32 TOTAL;
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u16 DROP;
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u8 active;
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u16 rpt_time;
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u8 ra_waiting_counter;
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u8 ra_pending_counter;
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u8 ra_drop_after_down;
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#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */
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u8 pt_active; /* on or off */
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u8 pt_try_state; /* @0 trying state, 1 for decision state */
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u8 pt_stage; /* @0~6 */
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u8 pt_stop_count; /* Stop PT counter */
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u8 pt_pre_rate; /* @if rate change do PT */
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u8 pt_pre_rssi; /* @if RSSI change 5% do PT */
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u8 pt_mode_ss; /* @decide whitch rate should do PT */
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u8 ra_stage; /* @StageRA, decide how many times RA will be done between PT */
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u8 pt_smooth_factor;
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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u8 rate_down_counter;
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u8 rate_up_counter;
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u8 rate_direction;
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u8 bounding_type;
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u8 bounding_counter;
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u8 bounding_learning_time;
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u8 rate_down_start_time;
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#endif
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};
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#endif
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struct ra_table {
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u8 firstconnect;
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/*@u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/
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#ifdef MU_EX_MACID
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u8 mu1_rate[MU_EX_MACID];
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#endif
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u8 highest_client_tx_order;
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u16 highest_client_tx_rate_order;
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u8 power_tracking_flag;
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u8 ra_th_ofst; /*RA_threshold_offset*/
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u8 ra_ofst_direc; /*RA_offset_direction*/
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u8 up_ramask_cnt; /*@force update_ra_mask counter*/
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u8 up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/
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u32 rrsr_val_init; /*0x440*/
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u32 rrsr_val_curr; /*0x440*/
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boolean dynamic_rrsr_en;
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#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
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u8 per_rate_retrylimit_20M[PHY_NUM_RATE_IDX];
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u8 per_rate_retrylimit_40M[PHY_NUM_RATE_IDX];
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u8 retry_descend_num;
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u8 retrylimit_low;
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u8 retrylimit_high;
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#endif
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u8 ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */
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void (*record_ra_info)(void *dm_void, u8 macid,
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struct cmn_sta_info *sta, u64 ra_mask);
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};
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/* @1 ============================================================
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* 1 Function Prototype
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* 1 ============================================================
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*/
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boolean phydm_is_cck_rate(void *dm_void, u8 rate);
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boolean phydm_is_ofdm_rate(void *dm_void, u8 rate);
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boolean phydm_is_ht_rate(void *dm_void, u8 rate);
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boolean phydm_is_vht_rate(void *dm_void, u8 rate);
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u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);
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u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);
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void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
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u32 *_out_len);
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void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
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void phydm_ra_dynamic_retry_count(void *dm_void);
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void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
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void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);
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void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
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u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
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void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val);
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void phydm_ra_info_watchdog(void *dm_void);
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void phydm_rrsr_en(void *dm_void, boolean en_rrsr);
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void phydm_ra_info_init(void *dm_void);
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void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
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u8 ra_th_ofst);
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u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
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u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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void phydm_update_hal_ra_mask(
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void *dm_void,
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u32 wireless_mode,
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u8 rf_type,
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u8 BW,
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u8 mimo_ps_enable,
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u8 disable_cck_rate,
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u32 *ratr_bitmap_msb_in,
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u32 *ratr_bitmap_in,
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u8 tx_rate_level);
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
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u8 phydm_get_plcp(void *dm_void, u16 macid);
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#endif
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void phydm_refresh_rate_adaptive_mask(void *dm_void);
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u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type);
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u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);
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void odm_ra_post_action_on_assoc(void *dm);
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u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect);
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void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx);
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void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc);
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void phydm_ra_offline(void *dm_void, u8 macid);
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void phydm_ra_mask_watchdog(void *dm_void);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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void odm_refresh_basic_rate_mask(
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void *dm_void);
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#endif
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#endif /*@#ifndef __PHYDMRAINFO_H__*/
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