63 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			63 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
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|  *
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|  * Copyright (C) 2011 Texas Instruments, Inc.
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|  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  */
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| #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
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| #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
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| 
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| /*
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|  * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
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|  */
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| #define SAR_BANK1_OFFSET		0x0000
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| #define SAR_BANK2_OFFSET		0x1000
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| #define SAR_BANK3_OFFSET		0x2000
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| #define SAR_BANK4_OFFSET		0x3000
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| 
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| /* Scratch pad memory offsets from SAR_BANK1 */
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| #define SCU_OFFSET0				0xfe4
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| #define SCU_OFFSET1				0xfe8
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| #define OMAP_TYPE_OFFSET			0xfec
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| #define L2X0_SAVE_OFFSET0			0xff0
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| #define L2X0_SAVE_OFFSET1			0xff4
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| #define L2X0_AUXCTRL_OFFSET			0xff8
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| #define L2X0_PREFETCH_CTRL_OFFSET		0xffc
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| 
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| /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */
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| #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04
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| #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET		0xa08
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| #define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET	0xe00
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| #define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET	0xe04
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| 
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| #define SAR_BACKUP_STATUS_OFFSET		(SAR_BANK3_OFFSET + 0x500)
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| #define SAR_SECURE_RAM_SIZE_OFFSET		(SAR_BANK3_OFFSET + 0x504)
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| #define SAR_SECRAM_SAVED_AT_OFFSET		(SAR_BANK3_OFFSET + 0x508)
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| 
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| /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
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| #define WAKEUPGENENB_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x684)
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| #define WAKEUPGENENB_SECURE_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x694)
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| #define WAKEUPGENENB_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6a4)
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| #define WAKEUPGENENB_SECURE_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6b4)
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| #define AUXCOREBOOT0_OFFSET			(SAR_BANK3_OFFSET + 0x6c4)
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| #define AUXCOREBOOT1_OFFSET			(SAR_BANK3_OFFSET + 0x6c8)
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| #define PTMSYNCREQ_MASK_OFFSET			(SAR_BANK3_OFFSET + 0x6cc)
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| #define PTMSYNCREQ_EN_OFFSET			(SAR_BANK3_OFFSET + 0x6d0)
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| #define SAR_BACKUP_STATUS_WAKEUPGEN		0x10
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| 
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| /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
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| #define OMAP5_WAKEUPGENENB_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x9dc)
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| #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0	(SAR_BANK3_OFFSET + 0x9f0)
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| #define OMAP5_WAKEUPGENENB_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0xa04)
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| #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1	(SAR_BANK3_OFFSET + 0xa18)
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| #define OMAP5_AUXCOREBOOT0_OFFSET		(SAR_BANK3_OFFSET + 0xa2c)
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| #define OMAP5_AUXCOREBOOT1_OFFSET		(SAR_BANK3_OFFSET + 0x930)
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| #define OMAP5_AMBA_IF_MODE_OFFSET		(SAR_BANK3_OFFSET + 0xa34)
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| #define OMAP5_SAR_BACKUP_STATUS_OFFSET		(SAR_BANK3_OFFSET + 0x800)
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| 
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| #endif
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