387 lines
9.3 KiB
C
Executable File
387 lines
9.3 KiB
C
Executable File
/*
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Digital Audio Interface(DAI) Controller register header
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Header file for DAI module register
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This file is the header file that define register for DAI module
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@file dai_reg.h
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@ingroup mIDrvAud_DAI
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@note Nothing
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Copyright Novatek Microelectronics Corp. 2016. All rights reserved.
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*/
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#ifndef _DAI_REG_H
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#define _DAI_REG_H
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#ifdef __KERNEL__
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#include "mach/rcw_macro.h"
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//#include "kwrap/type.h"
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#elif defined(__FREERTOS)
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#include "rcw_macro.h"
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#include "kwrap/type.h"
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#endif
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// Control Register
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REGDEF_OFFSET(DAI_CTRL_REG, 0x00)
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REGDEF_BEGIN(DAI_CTRL_REG)
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REGDEF_BIT(DAIEN, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(DMA_TX1_EN, 1)
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REGDEF_BIT(DMA_TX2_EN, 1)
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REGDEF_BIT(DMA_RX_EN, 1)
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REGDEF_BIT(DMA_TXLB_EN, 1)
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REGDEF_BIT(, 4)
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REGDEF_BIT(TX1_EN, 1)
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REGDEF_BIT(TX2_EN, 1)
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REGDEF_BIT(RX_EN, 1)
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REGDEF_BIT(TXLB_EN, 1)
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REGDEF_BIT(, 16)
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REGDEF_END(DAI_CTRL_REG)
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// Mode Configuration Register 0
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REGDEF_OFFSET(DAI_CONFIG_REG, 0x04)
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REGDEF_BEGIN(DAI_CONFIG_REG)
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REGDEF_BIT(EXCODEC_EN, 1)
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REGDEF_BIT(, 6)
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REGDEF_BIT(RX_SRC_MUX_SEL, 1)
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REGDEF_BIT(TX_MUX_SEL, 1)
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REGDEF_BIT(TX_MIXER, 1)
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REGDEF_BIT(, 2)
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REGDEF_BIT(HDMI_CH_SEL, 2)
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REGDEF_BIT(, 6)
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REGDEF_BIT(AVSYNC, 1)
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REGDEF_BIT(TXLB_SYNC, 1)
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REGDEF_BIT(, 2)
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REGDEF_BIT(AVSYNC_SRC, 3)
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REGDEF_BIT(, 5)
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REGDEF_END(DAI_CONFIG_REG)
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// I2S Mode Configuration Register
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REGDEF_OFFSET(DAI_I2SCONFIG_REG, 0x08)
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REGDEF_BEGIN(DAI_I2SCONFIG_REG)
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REGDEF_BIT(SLAVE, 1)
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REGDEF_BIT(I2S_ASFCK_INV, 1)
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REGDEF_BIT(, 2)
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REGDEF_BIT(CKRATIO, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(CHANNEL_LEN, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(I2SCKR_MATCH, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(I2SCKR_CUR, 3)
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REGDEF_BIT(, 1)
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REGDEF_BIT(I2S_ASFCK_OFS, 8)
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REGDEF_BIT(, 4)
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REGDEF_END(DAI_I2SCONFIG_REG)
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// Format Configuration Register 0
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REGDEF_OFFSET(DAI_FMTCFG0_REG, 0x10)
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REGDEF_BEGIN(DAI_FMTCFG0_REG)
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REGDEF_BIT(TX1_SOUNDM, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(TX1_SOUNDCH, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(TX1_PCMLEN, 2)
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REGDEF_BIT(, 1)
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REGDEF_BIT(TX1_DRAMCH, 1)
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REGDEF_BIT(, 4)
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REGDEF_BIT(TX2_SOUNDM, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(TX2_SOUNDCH, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(TX2_PCMLEN, 2)
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REGDEF_BIT(, 1)
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REGDEF_BIT(TX2_DRAMCH, 1)
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REGDEF_BIT(, 4)
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REGDEF_END(DAI_FMTCFG0_REG)
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// Format Configuration Register 1
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REGDEF_OFFSET(DAI_FMTCFG1_REG, 0x14)
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REGDEF_BEGIN(DAI_FMTCFG1_REG)
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REGDEF_BIT(RX_SOUNDM, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(RX_SOUNDCH, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(RX_PCMLEN, 2)
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REGDEF_BIT(, 1)
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REGDEF_BIT(RX_DRAMCH, 1)
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REGDEF_BIT(, 20)
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REGDEF_END(DAI_FMTCFG1_REG)
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// Format Configuration Register 2
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REGDEF_OFFSET(DAI_FMTCFG2_REG, 0x18)
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REGDEF_BEGIN(DAI_FMTCFG2_REG)
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REGDEF_BIT(TXLB_SOUNDM, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(TXLB_SOUNDCH, 2)
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REGDEF_BIT(, 2)
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REGDEF_BIT(TXLB_PCMLEN, 2)
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REGDEF_BIT(, 1)
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REGDEF_BIT(TXLB_DRAMCH, 1)
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REGDEF_BIT(, 20)
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REGDEF_END(DAI_FMTCFG2_REG)
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// Interrupt enable Register
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REGDEF_OFFSET(DAI_INTEN_REG, 0x20)
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REGDEF_BEGIN(DAI_INTEN_REG)
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REGDEF_BIT(TX1_DMABFI_INTEN, 1)
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REGDEF_BIT(TX2_DMABFI_INTEN, 1)
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REGDEF_BIT(RX1_DMABFI_INTEN, 1)
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REGDEF_BIT(RX2_DMABFI_INTEN, 1)
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REGDEF_BIT(TX1_DMALOAD_INTEN, 1)
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REGDEF_BIT(TX2_DMALOAD_INTEN, 1)
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REGDEF_BIT(RX_DMALOAD_INTEN, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(TX1_STOP_INTEN, 1)
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REGDEF_BIT(TX2_STOP_INTEN, 1)
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REGDEF_BIT(RX_STOP_INTEN, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(TX1_BWERR_INTEN, 1)
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REGDEF_BIT(TX2_BWERR_INTEN, 1)
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REGDEF_BIT(RX1_BWERR_INTEN, 1)
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REGDEF_BIT(RX2_BWERR_INTEN, 1)
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REGDEF_BIT(TX1_TCI_INTEN, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(RX_TCI_INTEN, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(RX_TCLATI_INTEN, 1)
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REGDEF_BIT(, 11)
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REGDEF_END(DAI_INTEN_REG)
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// Interrupt enable Register
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REGDEF_OFFSET(DAI_INTEN2_REG, 0x24)
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REGDEF_BEGIN(DAI_INTEN2_REG)
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REGDEF_BIT(TXLB_DMABFI_INTEN, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(TXLB_DMALOAD_INTEN, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(TXLB_STOP_INTEN, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(TXLB_BWERR_INTEN, 1)
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REGDEF_BIT(, 19)
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REGDEF_END(DAI_INTEN2_REG)
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// Interrupt status Register
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REGDEF_OFFSET(DAI_INTSTATUS_REG, 0x28)
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REGDEF_BEGIN(DAI_INTSTATUS_REG)
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REGDEF_BIT(TX1_DMABFI, 1)
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REGDEF_BIT(TX2_DMABFI, 1)
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REGDEF_BIT(RX1_DMABFI, 1)
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REGDEF_BIT(RX2_DMABFI, 1)
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REGDEF_BIT(TX1_DMALOAD, 1)
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REGDEF_BIT(TX2_DMALOAD, 1)
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REGDEF_BIT(RX_DMALOAD, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(TX1_STOP, 1)
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REGDEF_BIT(TX2_STOP, 1)
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REGDEF_BIT(RX_STOP, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(TX1_BWERR, 1)
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REGDEF_BIT(TX2_BWERR, 1)
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REGDEF_BIT(RX1_BWERR, 1)
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REGDEF_BIT(RX2_BWERR, 1)
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REGDEF_BIT(TX1_TCI, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(RX_TCI, 1)
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REGDEF_BIT(, 1)
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REGDEF_BIT(RX_TCLATI, 1)
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REGDEF_BIT(, 11)
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REGDEF_END(DAI_INTSTATUS_REG)
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// Interrupt status Register 2
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REGDEF_OFFSET(DAI_INTSTATUS2_REG, 0x2C)
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REGDEF_BEGIN(DAI_INTSTATUS2_REG)
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REGDEF_BIT(TXLB_DMABFI, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(TXLB_DMALOAD, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(TXLB_STOP, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(TXLB_BWERR, 1)
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REGDEF_BIT(, 19)
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REGDEF_END(DAI_INTSTATUS2_REG)
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// TX1 DMA starting address Register
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REGDEF_OFFSET(DAI_TX1DMASTART_REG, 0x40)
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REGDEF_BEGIN(DAI_TX1DMASTART_REG)
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REGDEF_BIT(TX1DMASTADR, 32)
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REGDEF_END(DAI_TX1DMASTART_REG)
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// TX2 DMA starting address Register
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REGDEF_OFFSET(DAI_TX2DMASTART_REG, 0x44)
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REGDEF_BEGIN(DAI_TX2DMASTART_REG)
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REGDEF_BIT(TX2DMASTADR, 32)
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REGDEF_END(DAI_TX2DMASTART_REG)
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// RX1 DMA starting address Register
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REGDEF_OFFSET(DAI_RX1DMASTART_REG, 0x48)
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REGDEF_BEGIN(DAI_RX1DMASTART_REG)
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REGDEF_BIT(RX1DMASTADR, 32)
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REGDEF_END(DAI_RX1DMASTART_REG)
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// RX2 DMA starting address Register
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REGDEF_OFFSET(DAI_RX2DMASTART_REG, 0x4C)
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REGDEF_BEGIN(DAI_RX2DMASTART_REG)
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REGDEF_BIT(RX2DMASTADR, 32)
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REGDEF_END(DAI_RX2DMASTART_REG)
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// TXLB DMA starting address Register
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REGDEF_OFFSET(DAI_TXLBDMASTART_REG, 0x50)
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REGDEF_BEGIN(DAI_TXLBDMASTART_REG)
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REGDEF_BIT(TXLBDMASTADR, 32)
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REGDEF_END(DAI_TXLBDMASTART_REG)
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// TX1 DMA RAM buffer size Register
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REGDEF_OFFSET(DAI_TX1DMABUFSIZE_REG, 0x60)
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REGDEF_BEGIN(DAI_TX1DMABUFSIZE_REG)
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REGDEF_BIT(TX1DMABUFSZ, 19)
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REGDEF_BIT(, 13)
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REGDEF_END(DAI_TX1DMABUFSIZE_REG)
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// TX2 DMA RAM buffer size Register
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REGDEF_OFFSET(DAI_TX2DMABUFSIZE_REG, 0x64)
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REGDEF_BEGIN(DAI_TX2DMABUFSIZE_REG)
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REGDEF_BIT(TX2DMABUFSZ, 19)
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REGDEF_BIT(, 13)
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REGDEF_END(DAI_TX2DMABUFSIZE_REG)
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// RX1 DMA RAM buffer size Register
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REGDEF_OFFSET(DAI_RX1DMABUFSIZE_REG, 0x68)
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REGDEF_BEGIN(DAI_RX1DMABUFSIZE_REG)
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REGDEF_BIT(RX1DMABUFSZ, 19)
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REGDEF_BIT(, 13)
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REGDEF_END(DAI_RX1DMABUFSIZE_REG)
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// RX2 DMA RAM buffer size Register
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REGDEF_OFFSET(DAI_RX2DMABUFSIZE_REG, 0x6C)
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REGDEF_BEGIN(DAI_RX2DMABUFSIZE_REG)
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REGDEF_BIT(RX2DMABUFSZ, 19)
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REGDEF_BIT(, 13)
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REGDEF_END(DAI_RX2DMABUFSIZE_REG)
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// TXLB DMA RAM buffer size Register
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REGDEF_OFFSET(DAI_TXLBDMABUFSIZE_REG, 0x70)
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REGDEF_BEGIN(DAI_TXLBDMABUFSIZE_REG)
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REGDEF_BIT(TXLBDMABUFSZ, 19)
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REGDEF_BIT(, 13)
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REGDEF_END(DAI_TXLBDMABUFSIZE_REG)
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// TX1 DMA RAM current address Register
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REGDEF_OFFSET(DAI_TX1DMACURRENT_REG, 0x80)
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REGDEF_BEGIN(DAI_TX1DMACURRENT_REG)
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REGDEF_BIT(TX1DMACUADR, 32)
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REGDEF_END(DAI_TX1DMACURRENT_REG)
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// TX2 DMA RAM current address Register
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REGDEF_OFFSET(DAI_TX2DMACURRENT_REG, 0x84)
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REGDEF_BEGIN(DAI_TX2DMACURRENT_REG)
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REGDEF_BIT(TX2DMACUADR, 32)
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REGDEF_END(DAI_TX2DMACURRENT_REG)
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// RX1 DMA RAM current address Register
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REGDEF_OFFSET(DAI_RX1DMACURRENT_REG, 0x88)
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REGDEF_BEGIN(DAI_RX1DMACURRENT_REG)
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REGDEF_BIT(RX1DMACUADR, 32)
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REGDEF_END(DAI_RX1DMACURRENT_REG)
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// RX2 DMA RAM current address Register
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REGDEF_OFFSET(DAI_RX2DMACURRENT_REG, 0x8C)
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REGDEF_BEGIN(DAI_RX2DMACURRENT_REG)
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REGDEF_BIT(RX2DMACUADR, 32)
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REGDEF_END(DAI_RX2DMACURRENT_REG)
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// TXLB DMA RAM current address Register
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REGDEF_OFFSET(DAI_TXLBDMACURRENT_REG, 0x90)
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REGDEF_BEGIN(DAI_TXLBDMACURRENT_REG)
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REGDEF_BIT(TXLBDMACUADR, 32)
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REGDEF_END(DAI_TXLBDMACURRENT_REG)
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// TX1 Time code offset value Register
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REGDEF_OFFSET(DAI_TX1TCOFFSET_REG, 0xA0)
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REGDEF_BEGIN(DAI_TX1TCOFFSET_REG)
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REGDEF_BIT(TX1TCOFST, 32)
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REGDEF_END(DAI_TX1TCOFFSET_REG)
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// TX1 Time code interrupt trigger value Register
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REGDEF_OFFSET(DAI_TX1TCTRIGGER_REG, 0xA4)
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REGDEF_BEGIN(DAI_TX1TCTRIGGER_REG)
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REGDEF_BIT(TX1TCITV, 32)
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REGDEF_END(DAI_TX1TCTRIGGER_REG)
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// TX1 Time code value Register
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REGDEF_OFFSET(DAI_TX1TCVALUE_REG, 0xA8)
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REGDEF_BEGIN(DAI_TX1TCVALUE_REG)
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REGDEF_BIT(TX1TCV, 32)
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REGDEF_END(DAI_TX1TCVALUE_REG)
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// RX Time code offset value Register
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REGDEF_OFFSET(DAI_RXTCOFFSET_REG, 0xB0)
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REGDEF_BEGIN(DAI_RXTCOFFSET_REG)
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REGDEF_BIT(RXTCOFST, 32)
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REGDEF_END(DAI_RXTCOFFSET_REG)
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// RX Time code interrupt trigger value Register
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REGDEF_OFFSET(DAI_RXTCTRIGGER_REG, 0xB4)
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REGDEF_BEGIN(DAI_RXTCTRIGGER_REG)
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REGDEF_BIT(RXTCITV, 32)
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REGDEF_END(DAI_RXTCTRIGGER_REG)
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// RX Time code value Register
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REGDEF_OFFSET(DAI_RXTCVALUE_REG, 0xB8)
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REGDEF_BEGIN(DAI_RXTCVALUE_REG)
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REGDEF_BIT(RXTCV, 32)
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REGDEF_END(DAI_RXTCVALUE_REG)
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//
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// Debug Mode Config Register
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//
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#define DAI_DBG_CONFIG_REG_OFS 0xC0
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REGDEF_BEGIN(DAI_DBG_CONFIG_REG)
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REGDEF_BIT(DBGEN, 1)
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REGDEF_BIT(, 3)
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REGDEF_BIT(EAC_DBG_EN, 1)
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REGDEF_BIT(EAC_DBG_MODE, 1)
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REGDEF_BIT(rsv, 26)
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REGDEF_END(DAI_DBG_CONFIG_REG)
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// Debug Mode Start Address Register
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#define DAI_DBG_ADDR_REG_OFS 0xC4
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REGDEF_BEGIN(DAI_DBG_ADDR_REG)
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REGDEF_BIT(DMASTADR, 31)
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REGDEF_BIT(, 1)
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REGDEF_END(DAI_DBG_ADDR_REG)
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// Debug Mode Buf Size Register
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#define DAI_DBG_SIZE_REG_OFS 0xC8
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REGDEF_BEGIN(DAI_DBG_SIZE_REG)
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REGDEF_BIT(DMABUFSZ, 19)
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REGDEF_BIT(, 13)
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REGDEF_END(DAI_DBG_SIZE_REG)
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// Debug Mode Status Register
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#define DAI_DBG_STS_REG_OFS 0xCC
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REGDEF_BEGIN(DAI_DBG_STS_REG)
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REGDEF_BIT(DONE, 1)
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REGDEF_BIT(, 31)
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REGDEF_END(DAI_DBG_STS_REG)
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// I2S TDM Data Order Register
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REGDEF_OFFSET(DAI_I2S_TDM_ORDER_REG, 0xD0)
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REGDEF_BEGIN(DAI_I2S_TDM_ORDER_REG)
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REGDEF_BIT(I2S_TDM_ORDER, 32)
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REGDEF_END(DAI_I2S_TDM_ORDER_REG)
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#endif
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