#ifndef __EAC_REG_H__ #define __EAC_REG_H__ #if defined(__FREERTOS) #include "rcw_macro.h" #include "kwrap/type.h"//a header for basic variable type #else #include "mach/rcw_macro.h" //#include "kwrap/type.h" #endif // EAC control register 0 REGDEF_OFFSET(EAC_CTRL0_REG, 0x00) REGDEF_BEGIN(EAC_CTRL0_REG) REGDEF_BIT(EAC_AD_EN, 1) REGDEF_BIT(EAC_DA_EN, 1) REGDEF_BIT(, 30) REGDEF_END(EAC_CTRL0_REG) // EAC control register 1 REGDEF_OFFSET(EAC_CTRL1_REG, 0x04) REGDEF_BEGIN(EAC_CTRL1_REG) REGDEF_BIT(LOAD, 1) REGDEF_BIT(, 31) REGDEF_END(EAC_CTRL1_REG) // EAC control register 2 REGDEF_OFFSET(EAC_CTRL2_REG, 0x08) REGDEF_BEGIN(EAC_CTRL2_REG) REGDEF_BIT(DMIC_EN, 1) REGDEF_BIT(DMIC_CLK_EN, 1) REGDEF_BIT(ADC_ALC_MODE, 1) REGDEF_BIT(DMIC_LR_SWAP, 1) REGDEF_BIT(DMIC2_LR_SWAP, 1) REGDEF_BIT(ADC_DMIC_CH, 1) REGDEF_BIT(, 1) REGDEF_BIT(ADC_ANALOG_RST_L, 1) REGDEF_BIT(ADC_ANALOG_RST_R, 1) REGDEF_BIT(ADC_ANALOG_LEFT_POW, 1) REGDEF_BIT(ADC_ANALOG_RIGHT_POW, 1) REGDEF_BIT(, 1) REGDEF_BIT(DAC_ANALOG_RST, 1) //REGDEF_BIT(DAC_ANALOG_LEFT_POW ,1) //REGDEF_BIT(DAC_ANALOG_RIGHT_POW ,1) REGDEF_BIT(, 11) REGDEF_BIT(PDREF_BUF, 1) REGDEF_BIT(PDREF_BIAS, 1) REGDEF_BIT(, 2) REGDEF_BIT(ADC_PG_EN, 1) REGDEF_BIT(DAC_PG_EN, 1) REGDEF_BIT(, 2) REGDEF_END(EAC_CTRL2_REG) /* ADC Related Registers */ // EAC ADC control register 0 REGDEF_OFFSET(EADC_CTRL0_REG, 0x10) REGDEF_BEGIN(EADC_CTRL0_REG) REGDEF_BIT(ADC_MIC_BIAS_EN, 1) //REGDEF_BIT(ADC_ANALOG_RES_INTERNAL,1) REGDEF_BIT(, 3) REGDEF_BIT(ADC_ANALOG_BOOST_L, 2) REGDEF_BIT(, 2) REGDEF_BIT(ADC_ANALOG_BOOST_R, 2) REGDEF_BIT(, 2) REGDEF_BIT(ADC_DCCAN_EN, 1) REGDEF_BIT(ADC_DCCAN_INIT_LOAD, 1) REGDEF_BIT(ADC_DCCAN_RESET, 1) REGDEF_BIT(, 1) REGDEF_BIT(ADC_DCCAN_RES, 4) REGDEF_BIT(, 4) REGDEF_BIT(ADCOUT_IIR_SEL_L, 1) REGDEF_BIT(ADCOUT_IIR_SEL_R, 1) REGDEF_BIT(ADCOUT_IIR2_SEL_L, 1) REGDEF_BIT(ADCOUT_IIR2_SEL_R, 1) REGDEF_BIT(ADC_MIC_BIAS_LVL, 1) REGDEF_BIT(, 3) //REGDEF_BIT(ALC_PEAK_SEL ,2) REGDEF_END(EADC_CTRL0_REG) // EAC ADC DCCAN INIT value register REGDEF_OFFSET(EADC_DCCAN_INIT_REG, 0x14) REGDEF_BEGIN(EADC_DCCAN_INIT_REG) REGDEF_BIT(DC_INIT_LEFT, 16) REGDEF_BIT(DC_INIT_RIGHT, 16) REGDEF_END(EADC_DCCAN_INIT_REG) // EAC ADC DCCAN Offset value register REGDEF_OFFSET(EADC_DCOFS_VAL_REG, 0x18) REGDEF_BEGIN(EADC_DCOFS_VAL_REG) REGDEF_BIT(DC_OFFSET_LEFT, 16) REGDEF_BIT(DC_OFFSET_RIGHT, 16) REGDEF_END(EADC_DCOFS_VAL_REG) // EAC ADC Volumn control register 0 REGDEF_OFFSET(EADC_VLMN0_REG, 0x20) REGDEF_BEGIN(EADC_VLMN0_REG) REGDEF_BIT(ADC_PGA_GAIN_LEFT, 5) REGDEF_BIT(, 3) REGDEF_BIT(ADC_PGA_GAIN_RIGHT, 5) REGDEF_BIT(, 3) REGDEF_BIT(ADC_DGAIN_LEFT, 8) REGDEF_BIT(ADC_DGAIN_RIGHT, 8) REGDEF_END(EADC_VLMN0_REG) // EAC ADC Volumn control register 1 REGDEF_OFFSET(EADC_VLMN1_REG, 0x24) REGDEF_BEGIN(EADC_VLMN1_REG) REGDEF_BIT(ADC_DGAIN2_LEFT, 8) REGDEF_BIT(ADC_DGAIN2_RIGHT, 8) REGDEF_BIT(, 16) REGDEF_END(EADC_VLMN1_REG) // EAC ALC Control config register 0 REGDEF_OFFSET(EALC_CFIG0_REG, 0x30) REGDEF_BEGIN(EALC_CFIG0_REG) REGDEF_BIT(ADC_ALC_EN, 1) REGDEF_BIT(ADC_NOISE_GATE_EN, 1) REGDEF_BIT(ADC_ZERO_CROSS_EN, 1) REGDEF_BIT(ADC_BOOST_D_EN, 1) REGDEF_BIT(ALC_IIR_SEL_L, 1) REGDEF_BIT(ALC_IIR_SEL_R, 1) REGDEF_BIT(ALC_BYPASS_SMTH_L, 1) REGDEF_BIT(ALC_BYPASS_SMTH_R, 1) REGDEF_BIT(ALC_STEP, 5) REGDEF_BIT(, 3) REGDEF_BIT(ALC_TARGET_L, 5) REGDEF_BIT(ALC_BOOST_COMPEN_L, 2) REGDEF_BIT(, 1) REGDEF_BIT(ALC_TARGET_R, 5) REGDEF_BIT(ALC_BOOST_COMPEN_R, 2) REGDEF_BIT(, 1) REGDEF_END(EALC_CFIG0_REG) // EAC ALC PGA Gain Clamp register 0 REGDEF_OFFSET(EALC_PGACFIG0_REG, 0x34) REGDEF_BEGIN(EALC_PGACFIG0_REG) REGDEF_BIT(ALC_MAXGAIN_L, 5) REGDEF_BIT(, 3) REGDEF_BIT(ALC_MINGAIN_L, 5) REGDEF_BIT(, 3) REGDEF_BIT(ALC_MAXGAIN_R, 5) REGDEF_BIT(, 3) REGDEF_BIT(ALC_MINGAIN_R, 5) REGDEF_BIT(, 3) REGDEF_END(EALC_PGACFIG0_REG) // EAC ALC Control config register 1 REGDEF_OFFSET(EALC_CFIG1_REG, 0x38) REGDEF_BEGIN(EALC_CFIG1_REG) REGDEF_BIT(ALC_ATTACK_TIME, 4) REGDEF_BIT(ALC_DECAY_TIME, 4) REGDEF_BIT(ALC_HOLD_TIME, 4) REGDEF_BIT(, 4) REGDEF_BIT(NG_ATTACK_TIME, 4) REGDEF_BIT(NG_DECAY_TIME, 4) REGDEF_BIT(NG_HOLD_TIME, 4) REGDEF_BIT(, 4) REGDEF_END(EALC_CFIG1_REG) // EAC ALC Resolution register 0 REGDEF_OFFSET(EALC_RESO0_REG, 0x3C) REGDEF_BEGIN(EALC_RESO0_REG) REGDEF_BIT(ALC_TRES, 23) REGDEF_BIT(, 9) REGDEF_END(EALC_RESO0_REG) // EAC ALC Noise Gate Configuration register 0 REGDEF_OFFSET(EALC_NGCFG0_REG, 0x40) REGDEF_BEGIN(EALC_NGCFG0_REG) REGDEF_BIT(NG_THRESHOLD_L, 5) REGDEF_BIT(, 3) REGDEF_BIT(NG_TARGET_L, 4) REGDEF_BIT(, 4) REGDEF_BIT(NG_THRESHOLD_R, 5) REGDEF_BIT(, 3) REGDEF_BIT(NG_TARGET_R, 4) REGDEF_BIT(, 4) REGDEF_END(EALC_NGCFG0_REG) // EAC ALC Noise Gate Configuration register 1 REGDEF_OFFSET(EALC_NGCFG1_REG, 0x44) REGDEF_BEGIN(EALC_NGCFG1_REG) REGDEF_BIT(NG_TRES, 23) REGDEF_BIT(, 9) REGDEF_END(EALC_NGCFG1_REG) // EAC zero crossing timeout control register REGDEF_OFFSET(EAC_ZCTC_REG, 0x48) REGDEF_BEGIN(EAC_ZCTC_REG) REGDEF_BIT(ZC_TIMEOUT, 12) REGDEF_BIT(, 20) REGDEF_END(EAC_ZCTC_REG) // EAC IIR Coeficient register 0 REGDEF_OFFSET(EAC_IIRCOF0_REG, 0x50) REGDEF_BEGIN(EAC_IIRCOF0_REG) REGDEF_BIT(IIR_B0_L, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF0_REG) // EAC IIR Coeficient register 1 REGDEF_OFFSET(EAC_IIRCOF1_REG, 0x54) REGDEF_BEGIN(EAC_IIRCOF1_REG) REGDEF_BIT(IIR_B1_L, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF1_REG) // EAC IIR Coeficient register 2 REGDEF_OFFSET(EAC_IIRCOF2_REG, 0x58) REGDEF_BEGIN(EAC_IIRCOF2_REG) REGDEF_BIT(IIR_B2_L, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF2_REG) // EAC IIR Coeficient register 3 REGDEF_OFFSET(EAC_IIRCOF3_REG, 0x5C) REGDEF_BEGIN(EAC_IIRCOF3_REG) REGDEF_BIT(IIR_A0_L, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF3_REG) // EAC IIR Coeficient register 4 REGDEF_OFFSET(EAC_IIRCOF4_REG, 0x60) REGDEF_BEGIN(EAC_IIRCOF4_REG) REGDEF_BIT(IIR_A1_L, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF4_REG) // EAC IIR Coeficient register 5 REGDEF_OFFSET(EAC_IIRCOF5_REG, 0x64) REGDEF_BEGIN(EAC_IIRCOF5_REG) REGDEF_BIT(IIR_A2_L, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF5_REG) // EAC IIR Coeficient register 6 REGDEF_OFFSET(EAC_IIRCOF6_REG, 0x68) REGDEF_BEGIN(EAC_IIRCOF6_REG) REGDEF_BIT(IIR_TOT_L, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF6_REG) // EAC IIR Coeficient register 7 REGDEF_OFFSET(EAC_IIRCOF7_REG, 0x70) REGDEF_BEGIN(EAC_IIRCOF7_REG) REGDEF_BIT(IIR_B0_R, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF7_REG) // EAC IIR Coeficient register 8 REGDEF_OFFSET(EAC_IIRCOF8_REG, 0x74) REGDEF_BEGIN(EAC_IIRCOF8_REG) REGDEF_BIT(IIR_B1_R, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF8_REG) // EAC IIR Coeficient register 9 REGDEF_OFFSET(EAC_IIRCOF9_REG, 0x78) REGDEF_BEGIN(EAC_IIRCOF9_REG) REGDEF_BIT(IIR_B2_R, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF9_REG) // EAC IIR Coeficient register 10 REGDEF_OFFSET(EAC_IIRCOF10_REG, 0x7C) REGDEF_BEGIN(EAC_IIRCOF10_REG) REGDEF_BIT(IIR_A0_R, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF10_REG) // EAC IIR Coeficient register 11 REGDEF_OFFSET(EAC_IIRCOF11_REG, 0x80) REGDEF_BEGIN(EAC_IIRCOF11_REG) REGDEF_BIT(IIR_A1_R, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF11_REG) // EAC IIR Coeficient register 12 REGDEF_OFFSET(EAC_IIRCOF12_REG, 0x84) REGDEF_BEGIN(EAC_IIRCOF12_REG) REGDEF_BIT(IIR_A2_R, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF12_REG) // EAC IIR Coeficient register 13 REGDEF_OFFSET(EAC_IIRCOF13_REG, 0x88) REGDEF_BEGIN(EAC_IIRCOF13_REG) REGDEF_BIT(IIR_TOT_R, 17) REGDEF_BIT(, 15) REGDEF_END(EAC_IIRCOF13_REG) // EAC Adjustment Registers REGDEF_OFFSET(EAC_ADJUST_REG, 0x90) REGDEF_BEGIN(EAC_ADJUST_REG) REGDEF_BIT(ADC_CLK_PHASE_INV, 1) REGDEF_BIT(, 3) REGDEF_BIT(DAC_CLK_PHASE_INV, 1) REGDEF_BIT(, 3) REGDEF_BIT(DMIC_DELAY_L, 3) REGDEF_BIT(, 1) REGDEF_BIT(DMIC_DELAY_R, 3) REGDEF_BIT(, 1) REGDEF_BIT(FT_TEST_DO_SEL, 1) REGDEF_BIT(, 15) REGDEF_END(EAC_ADJUST_REG) // EAC Current PGA Gain register REGDEF_OFFSET(EAC_CURPGA_REG, 0x94) REGDEF_BEGIN(EAC_CURPGA_REG) REGDEF_BIT(LEFT_CH, 5) REGDEF_BIT(, 3) REGDEF_BIT(LEFT_CH_UPDATE, 1) REGDEF_BIT(, 7) REGDEF_BIT(RIGHT_CH, 5) REGDEF_BIT(, 3) REGDEF_BIT(RIGHT_CH_UPDATE, 1) REGDEF_BIT(, 7) REGDEF_END(EAC_CURPGA_REG) // EAC Current noise floor register REGDEF_OFFSET(EAC_CURNF_REG, 0x98) REGDEF_BEGIN(EAC_CURNF_REG) REGDEF_BIT(ALC_CURNF_L, 16) REGDEF_BIT(ALC_CURNF_R, 16) REGDEF_END(EAC_CURNF_REG) /* DAC Related Registers */ // EAC DAC OUTPUT Control register REGDEF_OFFSET(EDAC_OUT_REG, 0xA0) REGDEF_BEGIN(EDAC_OUT_REG) REGDEF_BIT(, 4) REGDEF_BIT(ANALOG_LINEOUT_LEFT_EN, 1) REGDEF_BIT(ANALOG_LINEOUT_RIGHT_EN, 1) REGDEF_BIT(, 1) //REGDEF_BIT(ANALOG_SPK_EN, 1) REGDEF_BIT(DAC_SPK_MONO_EN, 1) REGDEF_BIT(, 24) REGDEF_END(EDAC_OUT_REG) // EAC DAC Control register 0 REGDEF_OFFSET(EDAC_CTRL0_REG, 0xA4) REGDEF_BEGIN(EDAC_CTRL0_REG) REGDEF_BIT(DAC_ZC_EN, 1) REGDEF_BIT(, 1) REGDEF_BIT(DAC_DATA_MIX, 1) REGDEF_BIT(, 1) REGDEF_BIT(DAC_DCCAN_EN, 1) REGDEF_BIT(DAC_DCCAN_INIT_LOAD, 1) REGDEF_BIT(, 2) REGDEF_BIT(DAC_OSR_SEL, 2) //REGDEF_BIT( ,2) //REGDEF_BIT(DWA_FORCE_ON ,1) REGDEF_BIT(, 10) REGDEF_BIT(ANALOG_TEST_EN, 1) REGDEF_BIT(ANALOG_DEPOP_EN, 1) REGDEF_BIT(, 2) REGDEF_BIT(DAC_DCCAN_RES, 4) REGDEF_BIT(, 4) REGDEF_END(EDAC_CTRL0_REG) // EAC DAC PGA Control register 0 //REGDEF_OFFSET(EDAC_PGA_REG ,0xA8) //REGDEF_BEGIN(EDAC_PGA_REG) // REGDEF_BIT( ,8) // REGDEF_BIT(DAC_PGA_LINEOUT ,5) // REGDEF_BIT( ,3) // REGDEF_BIT(DAC_PGA_SPK ,5) // REGDEF_BIT( ,11) //REGDEF_END(EDAC_PGA_REG) // EAC DAC Volume Control register REGDEF_OFFSET(EDAC_VLMN_REG, 0xAC) REGDEF_BEGIN(EDAC_VLMN_REG) REGDEF_BIT(DAC_DGAIN_LEFT, 8) REGDEF_BIT(DAC_DGAIN_RIGHT, 8) REGDEF_BIT(, 16) REGDEF_END(EDAC_VLMN_REG) // EAC DAC DCCAN INIT value register REGDEF_OFFSET(EDAC_DCCAN_INIT_REG, 0xB0) REGDEF_BEGIN(EDAC_DCCAN_INIT_REG) REGDEF_BIT(DC_INIT_LEFT, 16) REGDEF_BIT(DC_INIT_RIGHT, 16) REGDEF_END(EDAC_DCCAN_INIT_REG) // EAC DAC DCCAN Offset value register REGDEF_OFFSET(EDAC_DCOFS_VAL_REG, 0xB4) REGDEF_BEGIN(EDAC_DCOFS_VAL_REG) REGDEF_BIT(DC_OFFSET_LEFT, 16) REGDEF_BIT(DC_OFFSET_RIGHT, 16) REGDEF_END(EDAC_DCOFS_VAL_REG) // EAC DAC DEPOP Control register 0 REGDEF_OFFSET(EDAC_DPOP0_REG, 0xD0) REGDEF_BEGIN(EDAC_DPOP0_REG) REGDEF_BIT(CLK_HIGH_PERIOD, 12) REGDEF_BIT(CLK_LOW_PERIOD, 20) REGDEF_END(EDAC_DPOP0_REG) // EAC DAC DEPOP Control register 1 REGDEF_OFFSET(EDAC_DPOP1_REG, 0xD4) REGDEF_BEGIN(EDAC_DPOP1_REG) REGDEF_BIT(CYCLE_CNT, 12) REGDEF_BIT(, 20) REGDEF_END(EDAC_DPOP1_REG) // EAC DEBUG register 0 REGDEF_OFFSET(EAC_DBG0_REG, 0xF0) REGDEF_BEGIN(EAC_DBG0_REG) REGDEF_BIT(ALC_PEAK_DETECT, 1) REGDEF_BIT(, 3) REGDEF_BIT(ENB_FCP, 1) REGDEF_BIT(SEL_FCP, 2) REGDEF_BIT(, 25) REGDEF_END(EAC_DBG0_REG) /* DEBUG Related Registers */ // EAC DEBUG EN register REGDEF_OFFSET(EAC_DEBUG_REG, 0x104) REGDEF_BEGIN(EAC_DEBUG_REG) REGDEF_BIT(AD_DBG, 1) REGDEF_BIT(DA_DBG, 1) REGDEF_BIT(, 2) REGDEF_BIT(DBG_TYPE, 3) REGDEF_BIT(, 1) REGDEF_BIT(DBG_PORT_SEL, 4) REGDEF_BIT(, 20) REGDEF_END(EAC_DEBUG_REG) /* PHY Control */ // EAC PHY Control register REGDEF_OFFSET(EAC_PHYCTRL_REG, 0x100) REGDEF_BEGIN(EAC_PHYCTRL_REG) REGDEF_BIT(OS_ADC, 2) REGDEF_BIT(, 2) REGDEF_BIT(PD_EXT_RP_ADC, 1) REGDEF_BIT(PD_BIAS, 1) REGDEF_BIT(, 2) REGDEF_BIT(CS_COM_CTL, 2) REGDEF_BIT(CS_PGA_ADC, 2) REGDEF_BIT(CS_REF_ADC, 2) REGDEF_BIT(CS_SDM_ADC, 2) REGDEF_BIT(CS_COM_DAC, 2) REGDEF_BIT(CS_LN_DAC, 2) REGDEF_BIT(, 4) REGDEF_BIT(SW_POP_R, 1) REGDEF_BIT(SW_POP_L, 1) REGDEF_BIT(PD_V2I, 1) REGDEF_BIT(PD_OP_COM, 1) REGDEF_BIT(, 4) REGDEF_END(EAC_PHYCTRL_REG) /* iHome DAC IP CONTROL */ // EAC DAC IP Control 0 register REGDEF_OFFSET(EAC_DACIPCTRL0_REG, 0x140) REGDEF_BEGIN(EAC_DACIPCTRL0_REG) REGDEF_BIT(INV_DACIN, 1) REGDEF_BIT(SWAP_DACOUT, 1) REGDEF_BIT(DITHER_EN, 1) REGDEF_BIT(DITHER_TRI, 1) REGDEF_BIT(DITHER_LVL, 6) REGDEF_BIT(, 2) REGDEF_BIT(DAC_SCALE, 3) REGDEF_BIT(, 1) REGDEF_BIT(DAC_MUL_COEF, 5) REGDEF_BIT(, 11) REGDEF_END(EAC_DACIPCTRL0_REG) // EAC DAC IP Control 1 register REGDEF_OFFSET(EAC_DACIPCTRL1_REG, 0x144) REGDEF_BEGIN(EAC_DACIPCTRL1_REG) REGDEF_BIT(ADAC_DC_IN, 16) REGDEF_BIT(ZOHMD, 1) REGDEF_BIT(DSM3_GN, 2) REGDEF_BIT(LRP, 1) REGDEF_BIT(DWAL, 1) REGDEF_BIT(DWAR, 1) REGDEF_BIT(DSM3_L, 1) REGDEF_BIT(DSM3_R, 1) REGDEF_BIT(DAC2_PAGN, 6) REGDEF_BIT(RSVD, 2) REGDEF_END(EAC_DACIPCTRL1_REG) // EAC DMIC2 DCCAN INIT value register REGDEF_OFFSET(DMIC2_DCCAN_INIT_REG, 0x200) REGDEF_BEGIN(DMIC2_DCCAN_INIT_REG) REGDEF_BIT(DMIC2_DC_INIT_LEFT, 16) REGDEF_BIT(DMIC2_DC_INIT_RIGHT, 16) REGDEF_END(DMIC2_DCCAN_INIT_REG) // EAC DMIC2 DCCAN Offset value register REGDEF_OFFSET(DMIC2_DCOFS_VAL_REG, 0x204) REGDEF_BEGIN(DMIC2_DCOFS_VAL_REG) REGDEF_BIT(DMIC2_DC_OFFSET_LEFT, 16) REGDEF_BIT(DMIC2_DC_OFFSET_RIGHT, 16) REGDEF_END(DMIC2_DCOFS_VAL_REG) // EAC DMIC2 Volume Control register REGDEF_OFFSET(DMIC2_VLMN_REG, 0x20C) REGDEF_BEGIN(DMIC2_VLMN_REG) REGDEF_BIT(DMIC2_DGAIN_LEFT, 8) REGDEF_BIT(DMIC2_DGAIN_RIGHT, 8) REGDEF_BIT(, 16) REGDEF_END(DMIC2_VLMN_REG) #endif